1 PHY 440 Lab14: Programmable Logic Design Techniques I The design of digital circuits is a multi-step process. Specs.It starts with specifications describing what the circuit must do.Defining what a circuit receives as inputs and the outputs it Inpts. & Outs.generates is the next step. Once these are known the designerhas to create a truth table, which lists what values the outputs Truth Tablewill have for each possible combination of input values. Oncethe truth table is written down, the designer has to derive Boolean Boolean Equat.equations that describe how each binary output can be computedfrom the binary inputs using logical operations such as AND, OR, Gate-level DesignNOT etc. Next, the Boolean equations are transformed into agate-level circuit schematic drawing. Each AND, OR etc. operation Simulate Circuitin the Boolean equation is replaced with a corresponding ANDgate, OR gate etc. in the schematics. Inputs and outputs of these Build digital circuitgates are wired to let the passage of binary results betweenlogical operations. Before building the circuit it is a good thing Debug Circuitto make sure that all previous steps have been completed correctly.It is done by manual or computer simulation. If successful, aphysical circuit is build. Real inputs are applied to the circuitand possible bugs, if any, are fixed. You already built and tested some simple digital circuits using transistor-transistor logic(TTL) devices, and a breadboard with the connections were made using wires. Please,recall Lab 12 and Lab 13 for more details. As you have probably realized, this method ofbuilding circuits is not quite convenient: not every type of TTL may be immediatelyavailable; wires are often plugged into the wrong place and a lengthy check must bemade to find the error; once the circuit works it has to be taken apart to make room forthe next circuit; and last but not the least relatively complex digital circuits of more than10-20 gates are practically impossible to be built and tested. These problems may beeased if a different approach is followed and more elaborated tools employed. The designof digital circuits may still begin by describing the truth table. The details of the logiccircuit needed to realize the truth table are, however, worked out by a logic-synthesisprogram and not by hand. The operation of the "virtual" circuit built is checked using asimulation program. If the circuit simulates correctly, the gates and wires are mapped intoa Field Programmable Gate Array (FPGA) using specialized place & route programs.FPGA contains logic gates and the means for interconnecting them within a singleIntegrated Circuit (IC). The programmed FPGA can be used independently or placed intoa larger circuit where it will perform its functions. In this Lab you will be using theXILINX Foundation Series 2.1i software tools to create and test logic designs that can bedownloaded into the XC4003E FPGA. To be successful in this Lab you should reviewLabs 12 & 13, Chapters 11 & 12 of DH and the Guides to the XILINX software andhardware posted on the PHY440 WWW site.2Problem 1. Create a digital circuit of a single AND gate and verify its truth table. To begin, click on the "XILINX" icon. This will bring up the Project ManagerWindow. Select the File --> New project menu item. Then, enter the project name (onyour choice), project directory (keep the default one), type of design flow (FoundationSeries 3.1i; Schematic), chip family(XC4000E), chip part number(4003EPC84) anddevice speed (default). Click OK to return to the Project Manager Window. In the Project Manager window click on the Schematic Editor button (see thescreenshot above) and a schematic editor window will appear (see below).3 Select the Mode --> Symbols menu item and the SC window will appear with a listof all type of gates/components we can use. Scroll the list of components in the SCwindow, click on AND2 (two-input AND gate), move the cursor into the drawing areaand drop the AND2 gate there. We need to get our inputs and outputs into the circuit aswell. To do this click on the Inputs button. A dialog window (see below) will appear inwhich you have to type the name and the type of each input and output.4 While we have entered the inputs and output terminals, we still need to add buffersbetween the terminals and the logic gate. The buffers indicate that the signals attached tothem will actually enter and exit the FPGA chip via its I/O pins. To add input and outputbuffers we select IBUF and OBUF symbols, respectively, from the SC symbol windowand drop them in the drawing area. The next step is to connect(wire) the input/outputs tothe AND gate. Select the Mode --> Draw Wires menu and do the wiring. A line willappear connecting the inputs/outputs to the gate as shown below. Now that the schematics is done, we need to check it for errors. First, selectOptions --> Create Netlist. This will activate a program that examines the schematicdrawing and generates a machine-readable netlist which describes what type of gatesare used (only one in our case) and how they are connected. Once it is done, selectOptions --> Integrity test to initiate an error check. The check should indicate there areno errors. Then save the schematics using the File --> Save menu item. Also, the netlistcreated must be exported in a format that other XILINX tools understand. First click onthe Options --> Export Netlist and then on the Open button. Finally, select File --> Exitto close the Schematic editor and go back to the Project Manager window. Now it is time to use the functional simulator to see if what we have entered is workingcorrectly. In the present case it is to check the truth table for the AND gate.Start the functional Simulator by clicking the corresponding button in the ProjectManager window. This brings up the Logic Simulator window. The first thing to do isadd the inputs and outputs of the logic circuit to the Waveform Viewer so we can see5what is happening as the circuit is simulated. Do this by selecting the Signal --> AddSignals.. menu item. The Component Selection for Waveform Viewer window willappear. Click on the one of the inputs to highlight it and then click on the Add button.Repeat it for the rest terminals. Then click on the Close button.Now the inputs and the output are displayed but nothing happens since the two
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