TPU: time functionsTime Processor Unit (TPU)TPUSlide 4TPU TimersTPU RegistersTPU Control RegistersSlide 8Slide 9Channel ProgrammingSlide 11Channel InitializationInput Capture ParametersInput Capture/Transition CounterMemory Map of ParametersGeneral Parameter Memory MapChannel Control OptionsChannel PriorityChannel Function ActivationHost SequenceTypical Initialization SequenceShared Register ModificationShared Register Modification Contd.Slide 24Output Compare (OC)Slide 26OC ProgrammingOutput CompareOC Channel Control OptionsOC Channel ControlSlide 31Other OC ParametersOC Output ParametersTPU: time functions•Input event detection•Output event generation•Pulse-rate sensing•Pulse-rate modulation•Pulse-width modulationTime Processor Unit (TPU)RCPUU-busSystemInterfaceUnit(USIU)SRAML-busSRAMU-busTPU TPUSerialCommADC ADCIMBTPUControls 16 channels (available as pins). Can observe events on these channels (input).Can generate events on these channels (output).Events: transitions to indicate some state.TPUIMB3Memory-mappedinterfaceSystemConfig.ChannelcontrolParameterRAMMicro-EnginechannelsChan 0Chan 1Chan 15TCR1TCR216-bitcountersTPU TimersTwo timers: TCR1 & TCR2 -- 16 bits eachTCR1 programmed in TPUMCR.TCR2 can be driven by an external clock.All channel events are created or capturedw.r.t. a timer.TPU RegistersTPU Module Configuration Register: TPUMCR0x30 40000TCR1P00: div by 101: div by 210: div by 411: div by 81:2supv8psck9Clock prescalar0: 321: 4TPU Control RegistersTPU Interrupt Configuration Register (TICR)0x30 40080:4CIRL5:7Channel interruptrequest level: 0-7.ILBS8:9TPU Control RegistersChannel Interrupt Enable Register (CIER)0x30 400aCh15Ch14Ch13Ch1Ch001 214 150: interrupt disabled1: interrupt enabledTPU Control RegistersChannel Interrupt Status Register (CISR)0x30 4020Ch15Ch14Ch13Ch1Ch001 214 15Channel interrupt status:0: interrupt not asserted1: interrupt assertedChannel Programming16 predefined functions.Input Capture: capture one or multiple transitions on an input pin.Channel 0Capture the time of the transitionChannel ProgrammingProgram as an output channel.Output Compare: generate an event on the output: a single output transition, a single pulse, or a continuous 50% duty cycle pulse train.REF_TIME1offsetRef_Time = REF_TIME1 + offsetChannel InitializationChoose channel function: Code for IC: 0xAChannel function code for OC: 0x4Ch 15 Ch 14 Ch 13 Ch 120x30 400c: Channel Function Select Register 0 (CFSR0)Ch 11 Ch 10 Ch 9 Ch 80x30 400e: Channel Function Select Register 1 (CFSR1)Ch 7 Ch 6 Ch 5 Ch 40x30 4010: Channel Function Select Register 2 (CFSR2)Ch 3 Ch 2 Ch 1 Ch 00x30 4012: Channel Function Select Register 3 (CFSR3)Input Capture ParametersChannel Control (9 bits)MAX_COUNTTRANS_COUNTFINAL_TRANS_TIMELAST_TRANS_TIMEChannel W0x3041W00x3041W20x3041W40x3041W60x3041W80x3041WaInput Capture/Transition CounterInput Parameters:MAX_COUNT:The TPU raises an interrupt after counting as many events as MAX_COUNT.Output Parameters:TRANS_COUNT: current count of captured transitions.FINAL_TRANS_TIME: Timer time when the final transition (MAX_COUNTth ) is captured.LAST_TRANS_TIME: Timer time when the lasttransition (TRANS_COUNTth) is captured.Memory Map of ParametersChannel 0:MAX_COUNT: 0x30 4104TRANS_COUNT: 0x30 4106FINAL_TRANS_TIME: 0x30 4108LAST_TRANS_TIME: 0x30 410AGeneral Channel Y:MAX_COUNT: 0x30 41Y4TRANS_COUNT: 0x30 41Y6FINAL_TRANS_TIME: 0x30 41Y8LAST_TRANS_TIME: 0x30 41YAGeneral Parameter Memory MapP1 P2 P3 P4 P5 P6 P7 P8P1 P2 P3 P4 P5 P6 P7 P8P1 P2 P3 P4 P5 P6 P7 P8P1 P2 P3 P4 P5 P6 P7 P8Ch 0Ch 1Ch 2Ch 150x30410002 04 06 08 0a 0c 0e1012 14 16 08 1a 1c 1e2022 24 26 28 2a 2c 2ef0f2 f4 f6 f8 fa fc feChannel Control OptionsPart of channel initialization0:6TBS7:10Time Base Selection00xx: input channel000x: capture TCR1001x: capture TCR2PAC11:13Pin Action Control000:do not detect trans.001:detect rising edge010:detect falling edge011:detect either edge1xx:do not change PACPSC14:15Pin State Control11:do not force any state input pin01: force high10: force lowChannel PriorityChoose channel priority: 0:disable; 1:low; 2: medium; 3: high0x30 401c: Channel Priority Register 0 (CPR0)Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 80x30 401e: Channel Priority Register 1 (CPR1)Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0Channel Function ActivationAfter initializing channel, the channel function is activated by host service request, which can be further specialized through host sequence.0x30 4018: Host Service Request Register 0 (HSRR0)Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 80x30 401a: Host Service Request Register 1 (HSRR1)Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0Host Sequence0x30 4014: Host Sequence Register 0 (HSQR0)Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 80x30 4016: Host Sequence Register 1 (HSQR1)Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0Transition sequencing:x0: single shotx1: continualTypical Initialization Sequence•Disable the channel before programming it– CPR[ch]  00 (channel priority – disabled)•Assign the channel function–CFSR[ch]  0xA (for input capture/ITC)•Program the function parameters–MAX_COUNT=1 for input capture–Channel control: TBS: 000x (input channel; capture TCR1); PAC: 001 (detect rising edge); PSC: 11 (do not force)–Host sequence single shot. Write 00 into HSQRR[ch]. –etc.•Initialize host service (activate the channel):–HSRR[ch]  01 (initialize TCR mode)•Enable the channel:–CPR[ch]  01, 10, 11Shared Register Modification0x30 401a: Host Service Request Register 1 (HSRR1)Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 000: Host service complete  by TPU channel01: Initialize TCR mode  by CPU ProgramModification of HSRR involves read-modify-write: lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0]) ori r6, r6, 0x1 sh r6, 0x401a(r5) // writeDoes it work?How many independent potential writers into HSRR1?Shared Register Modification Con td .00 00 10 00 00 11 01 00lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0])ori r6, r6, 0x1 sth r6, 0x401a(r5) // write00 00 10 00 00 11 01 0100 00 10 00 00 11 00 00We don’t really know what happens to ch 1-7 fields while we modify ch 0 field.Shared Register Modification Con td .Solution: into ch 1-7 fields, write something we are definitely not supposed to write.00 is written by only the TPU, no CPU program should legitimately write that value. li r6, 0x1 //00 00 00 00 00 00 01 sth r6, 0x401a(r5)00 00 10