Lecture 10 MPC 555 InterruptInterrupt System Design: Hardware issuesInterrupt System Design: Software IssuesMPC555 Interrupt OverviewPowerPC Internal I/O ModulesUIMB: U-bus to IMB InterfaceSlide 7External InterruptsUnified System Interface UnitInterrupt ControllerSlide 11USIU Internal Interrupt SourcesConnecting To PowerPC CoreSlide 14MPC555 Interrupt All TogetherMPC555 Interrupt SummaryRecall Software IssuesInterrupt Priority And CodesUSIU Internal interruptsUse SIVEC and IRQ TableMachine State RegisterPPC Exception RegistersSlide 23Enable Interrupt and Save Exception RegistersMPC555 Interrupt Example: Periodic Interrupt Timer (PIT)PICSR: Periodic Interrupt Control & Select RegisterPITC: PIT CounterPITR: Periodic Interrupt Timer RegisterPIT Block DiagramPIT InitializationPIT Initialization (corrected)1Lecture 10MPC 555 Interrupt2Interrupt System Design: Hardware issuesConnect interrupt sources to processor core.Determine ISR addresses using exception vector table.Help software determine interrupt source.Disable/enable interrupts.Mask interrupts.3Interrupt System Design: Software IssuesInterrupt setupSet up interrupt levelSet up exception vector tableSet up interrupt maskEnable interruptDevice-specific setupInterrupt ProcessingCreate/destroy stack frameSave/restore machine states and EPCMask interrupt (optional)Enable interrupt (optional)Save/restore registers contentsDetermine interrupt sourceDetermine ISR addressDevice-specific processing4MPC555 Interrupt OverviewInternal I/OProcessor CoreUSIUExternal I/OMPC555 Interrupt Sources:1. External I/O devices2. Internal I/O device3. From USIU inside (Unified System Interface unit)USIU includes interrupt controlhandlermemory2135PowerPC Internal I/O ModulesTPU3: Time Processor Units, 3rd version; versatile functions, e.g. counting pulsesMIOS1: Modular I/O System; QADC64: Queued Analog-to-digital converterTouCAN: Control Area Network, two-wire, up to 1Mbps and 40m; e.g. network inside vehicleQSMCM: Queued Serial Multi-channel ModuleIMB3 bus: Inter-Module BusTPU3 TPU3 MIOS1 QADC64 QADC64 TouCAN TouCAN QSMCMIMB3 Bus16UIPENDUIMB: U-bus to IMB Interface•UIMB: U-bus to IMB interface•UIPEND: Interrupt pending reg.•U-bus: Unified bus, connecting multiple internal buses•UMCR[IRQUX]: Enable level 7-31IMB3 BusU-Busaddr/dataOther busInterruptcontroller2328UMCR[IRQUX]7UIMB: U-bus to IMB InterfaceThe interface converts 32 interrupt levels on IMB3 Bus to 8 interrupt levels on U-BusLevel 0-6 to U-Bus level 0-6Level 7-31 to U-Bus level 7Interrupt handler reads full UIPEND through memory-mapped I/O8External InterruptsOther I/O device:Hard drive, video card, …IRQ[0]: connect to resetUSIUU-BUS88IRQ[0:7]externalIRQResetTimer1113249Unified System Interface UnitThe USIU controls system start-up, system initialization and operation, system protection, and the external system bus. MPC555 USIU functions:System configuration and protectionInterrupt controllerSystem reset monitoring and generationClock synthesizerPower managementExternal bus interface (EBI) controlMemory controllerDebug supportInternal I/OProcessor CoreUSIU10Interrupt ControllerUSIU4TimebaseClockPITPLLSW watchdogDecrementerSIPENDSIMASKSIVECInternal I/Othrough U-busExternal IRQNMI controlIREQresetDecr timerNote: External IRQ is controlled by SIEL – triggered by falling edge or low level11Interrupt ControllerSIPEND[0:31]: Interrupt pending registerHandler accesses SIPEND for source of interruptBits 0-15 record interrupt source; 16-31 reserved External IRQ[0:7]: accessing SIPEND is enoughInternal IMB3 device: further accessing UIPENDSIMASK: mask registerIf SIMASK[i]= 0, then SIPEND[i] is blockedSIMASK[0] = 0 has no effectSIVEC: interrupt vector registerIndex to exception vector tableAccessed by interrupt service routine (ISR)NMI control: non-maskable interrupt controlExternal IRQ[0] is non-maskableSW watchdog is non-maskable12USIU Internal Interrupt SourcesMPC 555 has a crystal of 4MHz or 20MHzTime base: timer interrupt based on the clock; cannot be resetReal-time clock: timer interrupt based on real-time clock (like a watch); cannot be resetPIT: Periodic interrupt timer – goes off every n cycles PLL change of lock: Phase lock loop, used to provide higher clock frequency; generate interrupt in abnormal situation, e.g. lost the lock of the clockSoftware watch dog: Used to monitor help avoid software deadlockDecrementer: Another timer interrupt, but is processed by a special handler (less overhead)13Connecting To PowerPC CoreMSR[EE]Vector tablen+0x100n+0x500n+0x900&SSR1SSR0Inst bufferinstaddrto memIREQNMIDecrementer5123instThree interrupt lines to processor core: IREQ, NMI, and DecrementerMSR[EE]: Enable external interrupt IREQ: External interruptNMI: Non-maskable interrupt (e.g. reset button is pushed)Decrementer: fast timer interruptOther processor components not shownFinally!14Connecting To PowerPC CoreRefers to three handlers for1. Maskable Interrupt2. Non-maskable interrupt3. Decrementer (low-overhead timer)When an interrupt happens, hardware:Waits for current inst to complete Saves MSR[EE] to SSR0, Clears MSR[EE]Saves PC to SSR1Transfer control to n+0x100, n+0x500, or n+0x900, respectivelyThe rest is left to software handlerAll I/O interrupts share the same interrupt handler15MPC555 Interrupt All Together5142316MPC555 Interrupt Summary L7 for 7-31UIPENDL0L1L2L3L4L5L6From IMB3 peripheralsI0External IRQ[0:7]I1 I2 I3 I4 I5 I6 I7I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7 reserved1631SIPENDI0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7 reserved1631SIMASKIRQPriority arbiter8-bit vector: SIVEC17Recall Software IssuesInterrupt setupSet up interrupt levelSet up exception vector tableSet up interrupt maskEnable interruptDevice-specific setupInterrupt ProcessingCreate/destroy stack frameSave/restore machine states and EPCMask interrupt (optional)Enable interrupt (optional)Save/restore registers contentsDetermine interrupt sourceDetermine ISR addressDevice-specific processing18Interrupt Priority And CodesSIVEC contains a 8-bit interrupt code or vector for each sourcePriority Int. source Int. Code0 (highest) IRQ[0] 0x01 Level 0 0x42 IRQ[1] 0x83 Level 1 0xC4 IRQ[2] 0x10… … …15 Level 7 0x3cHelp determine interrupt source19USIU Internal interruptsCome