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Lecture 11 MPC 555 Interrupt Programming DetailsProgramming Perspective on Interrupt StatesInterrupt InitializationRecognizing Interrupt RequestInterrupt Event SequenceSet Up Exception Vector TableInitializing MPC555 InterruptsExternal Interrupt Exception – PrologueExternal Interrupt Exception – Prologue (Continue)Slide 10External Interrupt Exception – EpilogueExternal Interrupt Exception – Epilogue (Continue)Set Up ISR AddressesSlide 14Initializing DeviceGeneral Initialization stepsSlide 17Initialization ExamplesWriting ISR in CSlide 20Slide 21Using C Bit FieldSlide 23USIU Interface In CSlide 25Slide 26Initialization in CSlide 28C Volatile QualifierSlide 30Slide 31SummaryWhat’s Next1Lecture 11MPC 555 InterruptProgramming Details2Programming Perspective on Interrupt StatesSIPEND: State of USIU interrupt levels and IRQ pins SIMASK: USIU interrupt maskSIVEC: Interrupt vector code UIPEND: State of IMB3 interrupt levelsMSR: Machine stateMSR[EE]: Enable/disable external interruptsMSR[RI]: Whether machine status is recoverableSSR0  PC of interrupted routineSSR1  MSR bits before interrupt(SRR0, SRR1: Machine status Save/Restore Registers)3Interrupt Initialization1. Module Specific InitializationPIT example: Set up PITC2. Level Assignment (for IMB3 or USIU interrupt sources)PIT example: Assign level value to PIRQ of PISCR (bits 0:7)Interrupt level = 4  PIRQ = b’00001000 = 0x08Using unique interrupt level reduces processing time3. Enable Interrupt at device-levelPIT example: Set PIE of PISCR (Bit 13)4. Set Appropriate Mask Bits in SIMASKPIT example: Interrupt Level = 4  Priority level = 9 Setting bit 9 of SIMASK5. Enable external interruptSetting MSR[EE] (and MSR[RI]) Bits4Recognizing Interrupt RequestAn interrupt request is served when1. External Interrupt is enabledMSR[EE] is setIf MSR[RI] is not set, interrupt may not return correctly2. The interrupt is not maskedThe mask bit in SIMASK is set3. The interrupt has the highest priority among all requested, unmasked interruptsLowest level in SIPEND has the highest priority5Interrupt Event Sequence1. Interrupt exception occurs2. Completes current inst3. Saves NPC and MSR to SRR0 and SRR14. Branches to exception vector address for interrupt1. Saves machine context SRR0:12. Set MSR[RI] and/or MSR[EE]3. Saves other context (registers)4. Determines interrupt source, usually by getting SIVEC code5. Branches to ISR; may negate the interrupt request6. Restores contexts7. Returns by executing “rfi”5. Restores return address, MSR, enable interrupts6. Resumes execution at original NPC in SRRSystem behavior Typical Software Steps6Set Up Exception Vector Table; using exception table base 0xfff00000; reset exception handler.section .abs.FFF00100b reset_exception; external interrupt exception handler .section .abs.FFF00500b external_interrupt_exception; decrementer handler.section .abs.FFF0900b decrementer_exceptionTell assembler to putthe following code at this absolute addressJump to the handler code for external interrupt exception;code can also be put here if it is small enough7Initializing MPC555 Interrupts ; minimal initialization for using PIT.equ A_SIUBASE 0x2F.equ SYPCR 0xC004init555:… ; prologue code not shownlis r3, A_SIUBASElis r4, 0xffffori r4, 0xff03sth r4, SYPCR(r3)… ; epilogue code not shownLoad base address for USIU registersSYPCR: system protection control reg• reset bit 28-29 to disable software watchdog8External Interrupt Exception – Prologue; STEP 1: SAVE "MACHINE CONTEXT"stwu sp, -36 (sp) stw r3, 24 (sp)mfsrr0 r3stw r3, 12 (sp) mfsrr1 r3stw r3, 16 (sp); STEP 2: make execution recoverable and enable; external interruptmtspr EIE, r3 Set MSR[EE] and MSR[RI] bits; others:• EIE: set MSR[EE] and MSR[RI]• EID: set MSR[RI] onlyCreate stack frame, saving r3, SRR0, SRR1• Must use r3 or some other GPR because SRR0:1 cannot be saved directly• MSR[EE] and MSR[RI] are cleared, i.e., Interrupt disabled and execution notrecoverable9External Interrupt Exception – Prologue (Continue); STEP 3: SAVE OTHER APPROPRIATE CONTEXTmflr r3 stw r3, 8 (sp) mfcr r3 stw r3, 20 (sp) stw r4, 28 (sp) stw r5, 32 (sp)stw r6, 36 (sp)Save LR and CR• LR will be changed when calling ISR• ISR will have branches that change CR• r3 is used because CR and LR cannot be saved into memory directlySave other registers• assume that any ISR uses only r3-r6• must save more if ISR is written in C10External Interrupt Exception – Prologue (Continue); STEP 4: DETERMINE INTERRUPT SOURCElis r3, SIVEC@ha lbz r3, SIVEC@l (r3)lis r4, IRQ_table@hori r4, r4, IRQ_table@ladd r4, r3, r4lwz r4, 0(r4)mtlr r4; STEP 5: BRANCH TO INTERRUPT HANDLERblrlLoad 8-bit SIVEC into r3• SIVEC here is a 32-bit constant 0x2FC01CSet up jump inst address in a jump table• use lis and ori to load IRQ table base• add offset to get the ISR address• move jump inst address to LRblrl: branch to address in LR and save PC+4 in LR• basically this is a function call using function pointer• at target address: b kth_isr_addr11External Interrupt Exception – Epilogue; STEP 6: RESTORE CONTEXTlwz r4, 28 (sp)lwz r5, 32 (sp)lwz r6, 36 (sp)lwz r3, 28 (sp) mtcrf 0xff, r3lwz r3, 20 (sp)mtlr r3Restore r4, r5, r6, which were savedin prologueRestore CR and LR• again use r3 as a bridge• CR and LR (and any other SPR) cannot be loaded directly with data from memory12External Interrupt Exception – Epilogue (Continue); STEP 6: RESTORE CONTEXT mtspr NRI, r3lwz r3, 12 (sp)mtsrr0 r3 lwz r3, 16 (sp) mtsrr1 r3lwz r3, 24 (sp) addi sp, sp, 36; STEP 7: RETURN TO PROGRAMrfi ; End of InterruptRestore SRR0, SRR1 and r3• again use r3 as a bridge in restoring SRR0 and SRR1• r3 is the first to be saved and the last one to be restoredrfi (return from interrupt):• restores MSR bits saved in SRR1• restores next-PC saved in SRR0 Clear MSR[RI] and MSR[EE]• cannot be interrupted from now on; • NRI: SPR for fast clearing MSR[EE] and MSR[RI]13Set Up ISR AddressesUse Jump table:IRQ_jump_table:b irq0_handler ; interrupt pin 0b level0_handler ; interrupt level 0b irq1_handler ; interrupt pin 1b level1_handler ; interrupt level …b irq7_handler ; interrupt pin 7b level7_handler ; interrupt level 7…irq0_hanlder: ; IRQ0 ISR put here…14Set Up ISR AddressesUse address tableIRQ_table:.long irq0_handler ; interrupt pin 0.long level0_handler ; interrupt level 0.long irq1_handler ; interrupt pin 1.long


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ISU CPRE 381 - Programming Details

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