ISU CPRE 381 - verilog (5 pages)

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verilog



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verilog

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Pages:
5
School:
Iowa State University
Course:
Cpre 381 - Cptr Org &Asmb Prog

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Levels of Description Introduction Switch Level Verilog HDL is a Hardware Description Language HDL HDL is a language used to describe a digital system for example a computer or a component of a computer Most popular HDLs are VHDL and Verilog For analog systems AHDL Mixed mode systems MAST HDL Sabre Verilog programming is similar to C programming VHDL programming is similar to PASCAL some say like Ada Is an IEEE standard layout of the wires resistors and transistors on an IC chip Easiest to synthesize very difficult to write not really used Gate Structural Level logical gates flip flops and their interconnection Very easy to synthesize a text based schematic entry system RTL dataflow Level The registers and the transfers of vectors of information between registers Most efficiently synthesizable level Uses the concept of registers with combinational logic Behavioral algorithmic Level Highest level of abstraction Description of algorithm without hardware implementation details easiest to write and debug most difficult to synthesize We will focus on the RTL and structural level in the lab 1 Why Use HDL NO OTHER CHOICE For large digital systems gate level design is dead Millions of transistors on a digital chip HDL offers the mechanism to describe test and synthesize such designs Impossible to design on a gate or transistor level Comments start with a for one line or to across several lines Describe a system by a set of modules equivalent to functions in C 3 Explanation 2 A first digital model in Verilog module simple Simple Register Transfer Level RTL example to demo Verilog The register A is incremented by one Then first four bits of B is set to not of the last four bits of A C is the and reduction of the last two bits of A declare registers and flip flops reg 0 7 A B reg C The two initial s and always will run concurrently initial begin stop at Will stop the execution after 20 simulation units 20 stop end These statements done at simulation time 0 since no k initial



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