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ISU CPRE 381 - achitecture

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• Instructions are bits• Programs are stored in memory — to be read or written just like data•PMmemory for data, programs, compilers, editors, etc.Stored Program Concept1• Fetch & Execute Cycle– Instructions are fetched and put into a special register– Bits in the register "control" the subsequent actions– Fetch the “next” instruction and continueProcessorMemorycompilers, editors, etc.Instructions:• Language of the Machine• More primitive than higher level languagese.g., no sophisticated control flow• Very restrictivee.g., MIPS Arithmetic Instructions2• We’ll be working with the MIPS instruction set architecture– similar to other architectures developed since the 1980's– used by NEC, Nintendo, Silicon Graphics, SonyDesign goals: maximize performance and minimize cost, reduce design timeArchitecture Specification• Data types: – bit, byte, bit field, signed/unsigned integers logical, floating point, character• Operations: – data movement, arithmetic, logical, shift/rotate, conversion, input/output, control, and system calls•# of operands: 3# o ope a ds– 3, 2, 1, or 0 operands• Registers: – integer, floating point, control• Instruction representation as bit stringsCharacteristics of Instruction Set• Complete– Can be used for a variety of application• Efficient– Useful in code generation• Regular– Expected instruction should existCtibl4•Compatible– Programs written for previous versions of machines need it• Primitive– Basic operations• Simple– Easy to implement• Smaller– ImplementationExample of multiple operands• Instructions may have 3, 2, 1, or 0 operands• Number of operands may affect instruction length• Operand order is fixed (destination first, but need not that way)add $s0, $s1, $s2 ; Add $s2 and $s1 and store result in $s0add $s0, $s1 ; Add $s1 and $s0 and store result in $s05add $s0, $s; dd $s a d $s0 a d sto e esu t $s0add $s0 ; Add contents of a fixed location to $s0add ; Add two fixed locations and store result Where operands are stored• Memory locations– Instruction include address of location• Registers– Instruction include register number• Stack location– Instruction opcode implies that the operand is in stackFixed register6•Fixed register– Like accumulator, or depends on inst– Hi and Lo register in MIPS• Fixed location– Default operands like interrupt vectorsMIPS arithmetic• All instructions have 3 operands• Operand order is fixed (destination first)Example:C code: A = B + CMIPS code:add $s0 $s1 $s27MIPS code:add $s0, $s1, $s2 (associated with variables by compiler)MIPS arithmetic• Design Principle: simplicity favors regularity. Why?• Of course this complicates some things...C code: A = B + C + D;E = F - A;MIPS code: add $t0, $s1, $s2add $s0, $t0, $s3b$4 $5 $08sub $s4, $s5, $s0• Operands must be registers, only 32 registers provided• Design Principle: smaller is faster. Why?– More register will slow register file down.• Instructions, like registers and words of data, are also 32 bits long– Example: add $t0, $s1, $s2– registers have numbers, $t0=9, $s1=17, $s2=18• Instruction Format:000000 10001 10010 01000 00000 100000Machine Language9op rs rt rd shamt functRegisters vs. MemoryControlInput• Arithmetic instructions operands must be registers, — only 32 registers provided• Compiler associates variables with registers• What about programs with lots of variables10Processor I/OControlDatapathMemoryInputOutputMemory Organization• Viewed as a large, single-dimension array, with an address.• A memory address is an index into the array• "Byte addressing" means that the index points to a byte of memory.08 bits of data11123456...8 bits of data8 bits of data8 bits of data8 bits of data8 bits of data8 bits of dataMemory Organization• Bytes are nice, but most data items use larger "words"• For MIPS, a word is 32 bits or 4 bytes.0481232 bits of data32 bits of data32 bits of data32 bits of dataRegisters hold 32 bits of data12• 232bytes with byte addresses from 0 to 232-1• 230words with byte addresses 0, 4, 8, ... 232-4• Words are alignedi.e., what are the least 2 significant bits of a word address?12...32 bits of dataAddressing within a word• Each word has four bytes• Which byte is first and which is last• Two Choices– Least significant byte is byte “0” -> Little Endian– Most significant byte is byte “0” -> Big Endian13...048120 1 2 34 5 6 78 9 10 11………………....048123 2 1 07 6 5 411 10 9 8……………….Addressing• Memory address for load and store has two parts– A register whose content are known– An offset stored in 16 bits • The offset can be positive or negative– It is written in terms of number of bytes – It is but in instruction in terms of number of words32 byte offset is written as 32 but stored as 814–32 byte offset is written as 32 but stored as 8• Address is content of register + offset • All address has both these components• If no register needs to be used then use register 0– Register 0 always stores value 0• If no offset, then offset is 0• Consider the load-word and store-word instructions,– What would the regularity principle have us do?– New principle: Good design demands a compromise• Introduce a new type of instruction format– I-type for data transfer instructions– other format was R-type for registerExample:l $t0 32($ 2)Machine Language15•Example: lw $t0, 32($s2)35 18 9 32op rs rt 16 bit number• Where's the compromise?Instructions• Load and store instructions• Example:C code: A[8] = h + A[8];MIPS code: lw $t0, 32($s3)add $t0, $s2, $t0sw $t0 32($s3)16sw $t0, 32($s3)• Store word has destination last• Remember arithmetic operands are registers, not memory!Our First Example• Can we figure out the code?swap(int v[], int k);{ int temp;temp = v[k]v[k] = v[k+1];v[k+1] = temp;}swap:muli $2, $5, 417,,add $2, $4, $2lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)jr $31So far we’ve learned:• MIPS— loading words but addressing bytes— arithmetic on registers only• InstructionMeaningadd $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1 $s2 $s3$s1 = $s2$s318sub $s1, $s2, $s3$s1 = $s2 –$s3lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1• Decision making instructions– alter the control flow,– i.e., change


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ISU CPRE 381 - achitecture

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