1• Instructions are bits• Programs are stored in memory —to be read or written just like data•• Fetch & Execute Cycle– Instructions are fetched and put into a special register– Bits in the register "control" the subsequent actions– Fetch the “next”instruction and continueProcessor Memorymemory for data, programs, compilers, editors, etc.Stored Program Concept2Instructions:• Language of the Machine• More primitive than higher level languagese.g., no sophisticated control flow• Very restrictivee.g., MIPS Arithmetic Instructions• We’ll be working with the MIPS instruction set architecture– similar to other architectures developed since the 1980's3Architecture Specification• Data types: – bit, byte, bit field, signed/unsigned integers logical, floatingpoint, character• Operations: – data movement, arithmetic, logical, shift/rotate, conversion, input/output, control, and system calls• # of operands: – 3, 2, 1, or 0 operands• Registers: – integer, floating point, control• Instruction representation as bit strings4Characteristics of Instruction Set• Complete– Can be used for a variety of application• Efficient– Useful in code generation• Regular– Expected instruction should exist• Compatible– Programs written for previous versions of machines need it• Primitive– Basic operations• Simple– Easy to implement• Smaller– Implementation5Example of multiple operands• Instructions may have 3, 2, 1, or 0 operands• Number of operands may affect instruction length• Operand order is fixed (destination first, but need not that way)add $s0, $s1, $s2 ; Add $s2 and $s1 and store result in $s0 add $s0, $s1 ; Add $s1 and $s0 and store result in $s0 add $s0 ; Add contents of a fixed location to $s0 add ; Add two fixed locations and store result6Where operands are stored• Memory locations– Instruction include address of location• Registers– Instruction include register number• Stack location– Instruction opcodeimplies that the operand is in stack• Fixed register– Like accumulator, or depends on inst– Hi and Lo register in MIPS• Fixed location– Default operands like interrupt vectors7Addressing• Memory address for load and store has two parts– A register whose content are known– An offset stored in 16 bits • The offset can be positive or negative– It is written in terms of number of bytes – It is but in instruction in terms of number of words– 32 byte offset is written as 32 but stored as 8• Address is content of register + offset • All address has both these components• If no register needs to be used then use register 0– Register 0 always stores value 0• If no offset, then offset is 08• Instructions, like registers and words of data, are also 32 bitslong– Example: add $t0, $s1, $s2– registers have numbers, $t0=9, $s1=17, $s2=18• Instruction Format:00000010001100100100000000100000op rs rt rdshamtfunctMachine Language9• Consider the load-word and store-word instructions,– What would the regularity principle have us do?– New principle: Good design demands a compromise• Introduce a new type of instruction format– I-type for data transfer instructions– other format was R-type for register• Example: lw$t0, 32($s2)35 18 9 32op rs rt 16 bit number• Where's the compromise?Machine Language10• Decision making instructions– alter the control flow,– i.e., change the "next" instruction to be executed• MIPS conditional branch instructions:bne$t0, $t1, Label beq$t0, $t1, Label • Example: if (i==j) h = i + j;bne$s0, $s1, Labeladd $s3, $s0, $s1Label:....Control11• A simple conditional execution• Depending on i==j or i!=j, result is differentConditional Execution12• We have: beq, bne, what about Branch-if-less-than?• New instruction:if $s1 < $s2 then$t0 = 1slt$t0, $s1, $s2 else $t0 = 0• Can use this instruction to build "blt$s1, $s2, Label" —can now build general control structures• Note that the assembler needs a register to do this,—there are policy of use conventions for registersControl Flow13• Small constants are used quite frequently (50% of operands) e.g., A = A + 5;B = B + 1;C = C -18;• Solutions? Why not?– put 'typical constants' in memory and load them. – create hard-wired registers (like $zero) for constants like one.• MIPS Instructions:addi$29, $29, 4slti$8, $18, 10andi$29, $29, 6ori$29, $29, 4• How do we make this work?Constants14• simple instructions all 32 bits wide• very structured, no unnecessary baggage• only three instruction formats• rely on compiler to achieve performance—what are the compiler's goals?• help compiler where we canop rs rt rd shamtfunctop rs rt 16 bit addressop 26 bit addressRIJOverview of MIPS15• Instructions:bne$t4,$t5,Label Next instruction is at Label if $t4 °$t5beq$t4,$t5,Label Next instruction is at Label if $t4 = $t5j Label Next instruction is at Label • Formats:• Addresses are not 32 bits —How do we handle this with load and store instructions?op rs rt 16 bit addressop 26 bit addressIJAddresses in Branches and Jumps16• Instructions:bne$t4,$t5,Label Next instruction is at Label if $t4°$t5beq$t4,$t5,Label Next instruction is at Label if $t4=$t5• Formats:• Could specify a register (like lwand sw) and add it to address– use Instruction Address Register (PC = program counter)– most branches are local (principle of locality)• Jump instructions just use high order bits of PC – address boundaries of 256 MBop rs rt 16 bit addressIAddress Handling17MIPS Instruction Format31 26 25 21 20 16 15 11 10 6 5 0JUMPJUMP ADDRESS31 26 25 21 20 16 15 11 10 6 5 0REG 1 REG 2BEQ/BNE/JBRANCH ADDRESS OFFSET31 26 25 21 20 16 15 11 10 6 5 0REG 1 REG 2SWSTORE ADDRESS OFFSET31 26 25 21 20 16 15 11 10 6 5 0REG 1 REG 2LWLOAD ADDRESS OFFSET31 26 25 21 20 16