Next Generation On-chip Communication NetworksSeongmoo Heo, Jason Kim, and Albert Ma6.893 Project Report (the first checkpoint)fheomoo,jasonkim,[email protected] to the constraints of VLSI scaling, future processorand system-on-chip designs will by necessity incorporateon-chip communication networks. In this paper, protocolsand signaling technologies are explored in the context offuture on-chip multiprocessors in the 100nm regime. Scal-ing trends for devices and wires are predicted and based onthese models, protocols and circuits are designed.Because future multiprocessor chips require differentnetwork functionalities, tasks, and data transfer proper-ties, design space for the new chip architecture is explored,including communication paradigm, data type, topology,switching technique, routing protocol, and node organi-zation. A working communication protocol and a well-defined network architectureare designed to serve the needof next generation multi-processor chips.At the 100nm regime, interconnectdelay becomesa ma-jor challenge and needs to be taken into account at all lev-els. High-speed low-power CMOS drivers, receivers, andrepeaters for global on-chip interconnection are designedand evaluated in terms of energy and delay. Our goal is2.7GHz speed, which is about 10 FO4 delays, under 1.2Vsupply.1 Related WorkA summary of scaling trends and issues are presentedin [13, 6]. Based on these scaling trends, many researchershave concluded the only scalable architectures in the bil-lion transistor era must consist of an array of processingnodes within a chip.[9, 7, 15]As MIMD architectures became popular in the 80’s, thenetworkthat providedthe communicationchannel betweenprocessing elements became an important design focus.Since the first generation of multicomputers, interconnectnetworks have been designed, specifically tailored to thedistinct features of each machine’s communication style.One obvious interconnect characteristic is topology, rang-ing from the most popular 2D mesh to the exotic 3D cube.For example, MIT Alewife and Stanford Dash both hada 2D mesh network, while Cray T3D and MIT J-machinehad a cube topology. There are other important characteris-tics as well such as switching technique, routing protocol,and node organization [2]. Also, some characteristics ofthe switch or the machine feature have been explored togive rise to new designs. For example, MIT Alewife ma-chine attempted to integrate shared memory with message-passing communication [8].The big difference between previous interconnect net-works and the one we propose to build is that we deal withon-chipcommunicationnetworks. Until now, process tech-nologies allowed only a few processors on a chip, givingopportunity to build a bus-based network and leaving lit-tle incentive to build a switch-based network. However,with process technology nearing 0.13m, designers beganto have billions of transistors at their disposal and multipletens of processors will be fabricated on chip. As a result,a switch-based network will rise to popularity. Then, thequestion is, what kind of a switch-based network will beappropriate? This question will be answered differentlythan in the past because the on-chip network should al-low close coupling to the processing element at very highswitching speeds and ,at the same time, deal with slowglobal interconnect delay at the future process. A very re-cent example of such an on-chip network is the communi-cation network on RAW [15].Low latency and low-power switching network also in-volves encoding and decoding of data at both ends of apoint-to-point network. The weight encoding [10] andphase modulation [11] technique are such examples.Simple invertershave been sufficientas a driver/receiverand a repeater for on-chip global interconnection previ-ously. Therefore, most of the earlier works on interfacecircuit designs focused on sizing problems of multi-stagebuffering to optimize for power [4].However, recently low-power design has become one ofthe most important design criterion in VLSI circuits andit was found that long global interconnection can spend1big chunks of total power. Therefore, There have beenmany research efforts on the field of low-power on-chipglobal signaling scheme. There are two main techniquesdeveloped. The first one focuses on reducing the voltageswing on wire [5, 1]. This scheme needs a special low-swing driver and a level converting receiver. The secondtechnique reduces power consumption by utilizing charge-sharing between bit-lines. Hui Zhang’s paper shows excel-lent reviews on current low-power drivers/receiver circuitdesigns [16].Until now, wire speed was not a main concern for on-chip interconnection designers. Even long wire delay wassignificantly faster than gate delay. However, many re-search works revealed that in the near future, global wirecannot keep up with the ever-growing speed of logic gate.It is expected that the RC delay of on-chip global wirewill increase by 2 times per generation due to the in-crease of die size and the difficulty of metal-line scaling[6]. Many works on off-chip high-speed electrical signal-ing have been done [3, 12], but there is little work done inon-chip high-speed for the future process.2 Methodology2.1 ProcessBased on the projections in [13], we generated spicedevice decks and Space[14] parameter decks. The spicedecks model the transistors, while the Space decks are usedin the calculation of wiring capacitances from layout. Thespice decks were generated through BPTM, which is pro-vided by the Device Group at UC Berkeley. The Spaceparameter decks were generated by hand.2.2 ProtocolAs a first step, design space for building network proto-col and architecture will be explored. Since the sole userof the network is a programmer, the network must be ableto handle the needs of the programmer and the surround-ing chip environment. This means that we need to sup-port message passing, both expected and unexpected, andshared memory. In addition, streaming data and I/O in-terrupts and transfers must also be supported. These sys-tems affect the type of data that will travel on the net-work and most importantly, the behavior of the network.As for topology and routing scheme, the design is set touse a 2D topology and a point-to-point crossbar intercon-nect. This is because 2D is most suited for scaling in VLSIon-chip and a point-to-point crossbar allows fast multi-cast/broadcast messages on the network. Two other
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