Abstract—A growing need for computational power in mobile devices has spawned increased interest in low-power microprocessors. Some low-power applications require very high performance, such as real-time video decoding on Personal Digital Assistants. A growing body of work has examined how to provide this high performance when needed, while throttling performance so that power consumption can drop to very low levels when performance is not required. Observing that the issue logic in an out-of-order microprocessor consumes a significant amount of power, several groups have attempted to modify this part of the processor so that it can dynamically enter a low-power mode. We have revisited these topics and our work shows that simple approaches to modifying issue logic fail to reduce the average energy per instruction. We also look at the possibility of including a low-power single-issue processor on the same die as a high-performance multiple-issue processor. Swapping between these two processors allows a dynamic tradeoff between power and performance, but we show that this approach also struggles to reduce the average energy per instruction in the low-power mode. Index terms—Issue Window, Issue Logic, Out-of-Order, Low Power, Power/Performance Throttling I. INTRODUCTION Much of the thrust of recent computer architecture work has been in search of increased performance. As transistor budgets have increased, more and more technologies from mainframes were incorporated in microprocessor designs. The product of this evolution was high performance microprocessors that sacrificed power consumption to maximize performance. With the emerging importance of low-power markets, these speed demons have been retrofitted to consume less power by incorporating clock gating, voltage scaling, and more recently, dynamic resizing of key architectural features such as the issue window. Many existing techniques for reducing power are well established and extremely effective, including dynamically reconfiguring the cache[1] and voltage scaling[2]. Reducing the supply voltage of a microprocessor has a roughly linear effect on performance (due to weaker electric fields) but a squared effect on power dissipation (since power consumption is proportional to ½*frequency*CV2). The authors are graduate students at the Massachusetts Institute of Technology, Cambridge, MA. Voltage scaling must be taken into account when comparing two architectures for power efficiency. It is tempting to use a metric such as energy/instruction or the power delay product, however, one must also take into account the required performance level. A processor with seemingly poor energy/instruction characteristics that has more performance than required can be run at a lower voltage thus reducing performance and reducing the energy/instruction. While voltage scaling is a very good way of providing additional power/performance modes, it has its limits. When operating voltage approaches the threshold voltage of the transistors, the performance of the transistors begins dropping off much faster than linearly. As threshold voltages are reduced, leakage currents increase, which, in turn, increases power consumption. The Semiconductor Industry Association predicts that in the year 2005, supply voltages for low power applications will be 0.9-1.2V [3], compared to a typical modern supply of 1.2V for a low-power processor like the Transmeta Crusoe. This implies a very limited ability for processors to exploit voltage scaling dynamically in order to scale power/performance. Clearly there is a need for additional power/performance throttling mechanisms. Other mechanisms for throttling performance, such as disabling portions of the cache, also have drawbacks; if the cache is made too small, the increasing miss rate will cause more power to be consumed by requiring main memory accesses. It has been observed that one major power drain in modern out-of-order processors is the issue logic; every clock cycle, each instruction in the issue queue must be checked to see if it can be dispatched. Retired instructions broadcast the availability of new operands on long bit lines across the entire issue window. Some processors, such as the Alpha 21264, compact the issue queue in order to implement an oldest-first priority algorithm, and this process requires even more energy. In the 21264, between 18 and 46 percent of the total power of the processor is consumed by the issue logic [4]. In light of this, methods of scaling back the size of the issue window and the number of instructions issued each cycle have been proposed in order to reduce power consumption at the cost of reduced performance.[5,6] These methods are compatible with cache disabling and voltage scaling; for maximum reduction in power consumption the power management software could simultaneously reduce the Issue Logic and Power/Performance Tradeoffs Edwin Olson [email protected], Andrew Menard [email protected] to the lowest possible level, disable parts of the cache, and reduce the issue window size, or it could find intermediate power/performance points by doing only one or two of these optimizations, possibly by analyzing the type of code that is running to determine how much cache it needs or how much its performance would benefit from a large issue window. We also consider an alternate scheme of bypassing complex issue logic completely. We propose to do this by placing an in-order, single-issue core alongside the out-of-order multiple-issue core, with the OS able to swap between them, thus avoiding the complex out-of-order issue logic completely. Several studies have shown that relatively simple modifications can allow an operating system to do performance throttling without spending an excessive amount of time profiling the code being executed, [7] and that relatively simple hardware structures can also monitor performance needs [5]. Thus, the power overhead required for dynamic throttling is minimal, which is necessary for it to be useful. Any overhead necessary to implement the strategies described in this paper is ignored from a power perspective; we assume that dynamic reconfigurations are perfectly efficient. Since we will demonstrate that these strategies do not reduce power, the omission of the overhead energy would only make the strategies even more unappealing. II. METHODOLOGY In order to conduct our study, we needed to measure the impact of
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