1The End of Conventional MicroprocessorsEdwin Olson9/21/2000Historical Growth• Microprocessor speed increasing at a roughly 50-60% annual rate. – Moore’s law predicts about 58%• Improving manufacturing processes responsible– Transistors switch faster– Increasing transistor budget enables more sophisticated architectures2Two Ways to Achieve Performance• Braniacs: High IPC, lower clock-rate (higher FO4 delay) processors like PA-RISC• Speed Demons: Low IPC, high clock-rate (lower FO4 delay) processors like Alpha.• Today’s designs have benefited from both approaches, which exemplifies the headroom available today in both strategies.Today’s uPs• Today’s uPs are monolithic cores which assume that signals can reach entire chip in one clock. They are capacity bound.• In 0.18um, signals may not be able to travel from one corner to another in 1 cycle. uPsbegin to become communication bound. •WHY?3Transistor Scaling• Good News! Switching delay of transistor SURSRUWLRQDO WR ! • FO4 delay empirically estimated by– 360*2 ps (2 is minimum gate length)• 0.250 : 90ps• 0.035nm: 12.6ps• This is a 7.1x speed improvement.Wire Delay• Model a wire as a distributed RC network• Many RC delays in parallelV2021LRCxdxRCwwLww ==∫τCw: Capacitance per unit lengthRw: Resistance per unit length4Wire Scaling• Assume we scale an existing design down, VKULQNLQJ DOO GLPHQVLRQV E\ •Cw N0W/d (W is width of wire)• When scaled by ( <1), – W => W– d => G–Cwstays the same!– 5 ! 52(assuming fixed aspect ratio)• Not quite this bad if we can increase aspect ratio some– / ! /– ! • A wire is the same speed as before.2021LRCxdxRCwwLww ==∫τWire Scaling• Suppose we make our design more complex (to increase IPC). Now, L doesn’t scale.•Now,This does not account for increasing aspect ratios and falling resistivities. τατ21→5Side note• We can design a wire with delay proportional to just L, not L2by using repeaters.• Given a process-determined repeater-length, l0, we can span a distance of L by having repeater segments joined together. Each repeater segment has a delay proportional to l022.RepeatersV VRwCwRrCrRwRwRwCwCwCwl0()()++++=++++∫)(21002000000rwrrwwwrwrlrwwRlRClRClRClLRlRCdxRxRClLρρCr=Cap. of RepeaterRr=Res. Of RepeaterCw=Cap/length of wireRw=Res/length of wire LQWULQVLF GHOD\ RI repeater6Gates vs. WiresSource: SIA 1999 Roadmap1/ 21/ 2constantSo what’s the problem?• Transistors are getting faster• Local wiring is staying the same speed• Global wiring is getting really slow • Smaller feature size only improves transistor speed. Even if the wires were infinitely fast, projected process improvements (250nm to 35nm) would yield only a 7.2x improvement through 2014 (15% annualized growth).•We need global wiring to access caches and other large structures!7Material Science to the RescueGate (nm) Dielectric (k)Metal ( )250 3.9 3.3180 2.7 2.2130 2.7 2.2100 1.6 2.270 1.5 1.850 1.5 1.835 1.5 1.8C/Fl doped SiO2SiO2Xerogel/FluroPolymer/Porous CVD Carbon-doped SiO2AlCuCu improvementsPorous Dielectrics/Air Gap (Vacuum=1)Approaches to Scaling uP designs• We can’t increase IPC and clock rate.– IPC increased by bigger structures, which are getting slower, not faster.• Capacity Scaling: shrink structures so that they have roughly constant access penalties• Pipeline Scaling: fix structure size, and increase pipeline depth to account for growing latency.8FO4 delaysCapacity and Pipeline Scaling9Capacity and Pipeline Scaling-- PerformanceAgarwal’s Results• Maximum speedup of 7.4 (annual gain of 12.5%)• BUT the model they used has– large branch-taken penalties– does not use any clustering– Does not account for advances in compilers, microarchitecture (e.g., VLIW)10Have we really just now hit the wall?Fastest uPFastest machinesSource: Jim Smith, ISCA 2000 Panel
View Full Document
Unlocking...