1Sparc ArchitectureCS217CourseOutline• FirstfourweeksCprogramming• SecondfourweeksMachinearchitecture• ThirdfourweeksUnixoperatingsystem2CompilationPipeline• Compiler(gcc):.c .s– translateshigh-levellanguagetoassemblylanguage• Assembler(as):.s .o– translatesassemblylanguagetomachinelanguage• Archiver(ar):.o .a– collectsobjectfilesintoasinglelibrary• Linker(ld):.o + .a a.out– buildsanexecutablefilefromacollectionofobjectfiles• Execution(execlp)– loadsanexecutablefileintomemoryandstartsitExampleCompilation• High-levellanguagex=a+b;• Assemblylanguagelda,%r1ldb,%r2add%r1,%r2,%r3st %r3,x• Machinelanguage110000100000...SymbolicRepresentationBit-encodedRepresentation3MachineArchitectureControlUnitCacheRegistersALUFPUCPUMemoryDisk Net DisplayMBusI/OBusStorageHierarchy• Registers~128,1-5nsaccesstime(CPUcycletime)• Cache1KB– 4MB,20-100ns(multiplelevels)• Memory64MB– 2GB,200ns• Disk1GB– 100GB,10ms• Long-termStorage1TB,1-10s4Outline• Instructionexecution• Accessingregisters• Accessingmemory• Instructionformats• etc.InstructionExecution• CPU’scontrolunitexecutesaprogramPC memorylocationoffirstinstructionwhile(PC!=last_instr_addr)execute(MEM[PC]);• Multiplephases…fetch: instructionfetch;incrementPCdecode: interpretinstructionformatoperandfetch: loadoperandsintoregistersexecute: performinstructionopcodestore: writeresultstomemory5InstructionPipelining• Pipeline• PC isincrementedby4attheFetch stagetoretrievethenextinstruction...Fetch Decode Oprnd Execute StoreFetch Decode Oprnd Execute StoreFetch Decode Oprnd Execute StoreSparcRegisters• 32x 32-bitgeneral-purposeregisters%r0…%r31• Registermap%g0…%g7%r0…%r7 global%o0…%o7%r8…%r15 output%l0…%l7%r16…%r23 local%i0…%i7%r24…%r31 input• Someregistershavededicateduses%sp(%r14,%o6) stackpointer%fp (%r30,%i6) framepointer%r15 temporary%r31 returnaddress%g0(%r0) always 06SparcRegisters(cont)• Special-purposeregistersmanipulatedbyspecialinstructions• Examplesfloatingpointregisters(%f0…%f31)programcounter (PC)nextprogramcounter (NPC)integercodition codes (PSR)trapbaseregister (TBR)window (WIM)etc.Instructions• Eachmachineinstructioniscomposedof…opcode: operationtobeperformedoperand: datathatisoperatedupon• Eachmachinesupportsafewformats…opcodeopcodedstopcodesrcdstopcode src1src2dst7SparcInstructionSet• Instructiongroupsintegerarithmetic(add,sub,...)bit-wiselogical(and,or,xor,...)bit-wiseshift(sll,srl,...)load/store(ld, st,...)integerbranch(be,bne,bl,bg,...)Trap(ta,te,...)controltransfer(call,save,...)floatingpoint(ldf,stf,fadds,fsubs,...)floatingpointbranch(fbe,fbne,fbl,fbg,...)SparcInstructionSet• InstructionformatsFormat1(op=1)-- e.g.,callFormat2(op=0):-- e.g.,branchesFormat3(op=2or3):-- e.g.,addop31 298Sparc InstructionSet• Format3(op=2or 3):31 29 24 18 13 12 4oprd op3 rs1 ignore0 rs2add%i1,%i2,%o2Sparc InstructionSet• Format3(op=2or 3):31 29 24 18oprd op3 rs1 simm1313112 4oprd op3 rs1 ignore0 rs2ORsimm13isasignedconstantwithin+-4096add%i1,360,%o29Example• AssemblyLanguageadd%i1,360,%o2• Machinelanguage1001010000000110011000010110100031 29 24 18212 0 31 55013112210 0 25 3601(decimal)(octal)Other Sparc Instructions• Format1(op=1)-- e.g.,call• Format2 (op=0)-- e.g.,branchesop disp3031 29oprd op2 imm22opa cond op2 disp2231 29 28 24 2110AddressingMemory• 8-bitbyteisthesmallestaddressableunit• 32-bitaddresses;thus32-bitaddressspace• Canloadandstoredoublewords too• Sparc isbig-endianAA A+1 A+2 A+3A A+17 01531bytehalfwordwordAddressingMemory• Twomodestoyieldeffectiveaddressaddcontentsoftworegistersld[%o1],%o2registerindirectst %o1,[%o2+%o3]registerindexedaddcontentsofregisterandimmediateld[%o1+10],%o2basedisplacement11UpcomingLectures...• Instructionset• Numbersystems• Branchingconditioncodes• Procedurecalls• Assembler• Linker•
View Full Document