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Princeton COS 217 - Assemblers and Linkers

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1 1 Assemblers and Linkers!2 Goals for this Lecture!• Help you to learn about:"• IA-32 machine language"• The assembly and linking processes"2 3 Why Learn Machine Language!• Machine language is the last stop on the “language levels” tour"• A power programmer knows about the relationship between assembly language and machine language"• A systems programmer knows how an assembler translates assembly language to machine language"4 Part 1: Machine Language"3 5 IA-32 Machine Language!• IA-32 machine language"• Difficult to generalize about IA-32 instruction format"• Many (most!) instructions are exceptions to the rules"• Generally, instructions use the following format shown in following slides"• Weʼll go over"• The format of instructions"• Two example instructions"• Just to give a sense of how it works…"6 IA-32 Instruction Format!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 Instruction prefix"• Sometimes a repeat count"• Rarely used; donʼt be concerned"4 7 IA-32 Instruction Format (cont.)!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 Opcode"• Specifies which operation should be performed"• Add, move, call, etc."8 IA-32 Instruction Format (cont.)!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 ModR/M"• Specifies types of operands (immediate, register, memory)"• Specifies sizes of operands (byte, word, long)"• Sometimes denotes a register:$000 = EAX/AL; 011 = EBX/BL; 001 = ECX/CL; 010 = EDX/DL;$110 = ESI/DH; 111 = EDI/BH; 101 = EBP/CH; 110 = ESP/AH "• Sometimes contains an extension of the opcode"5 9 IA-32 Instruction Format (cont.)!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 SIB"• Used when one of the operands is a memory operand$that uses a scale, an index register, and/or a base register"10 IA-32 Instruction Format (cont.)!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 Displacement"• Used in jump and call instructions"• Indicates the displacement between the destination instruction$and the jump/call instruction"• More precisely, indicates:$[addr of destination instr] – [addr of instr following the jump/call]"• Uses little-endian byte order"6 11 IA-32 Instruction Format (cont.)!Instruction prefixes Opcode ModR/M SIB Displacement Immediate Up to 4 prefixes of 1 byte each (optional) 1, 2, or 3 byte opcode 1 byte (if required) 1 byte (if required) 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes Mod Reg/ Opcode R/M 7 6 5 3 2 0 Scale Index Base 7 6 5 3 2 0 Immediate"• Specifies an immediate operand"• Uses little-endian byte order"12 Example: Push on to Stack !• Assembly language:$" "pushl %edx ""• Machine code:"• IA32 has a separate opcode for push for each register operand"• 50: pushl %eax"• 51: pushl %ecx"• 52: pushl %edx"• …"• Results in a one-byte instruction"• Observe: sometimes one assembly language instruction can map to a group of different opcodes"0101 00107 13 Example: Load Effective Address!• Assembly language:$" "leal (%eax,%eax,4), %eax ""• Machine code:"• Byte 1: 8D (opcode for “load effective address”)"• Byte 2: 04 (dest %eax, with scale-index-base)"• Byte 3: 80 (scale=4, index=%eax, base=%eax)"1000 1101 0000 0100 1000 0000 Load the address %eax + 4 * %eax into register %eax 14 CISC and RISC!• IA-32 machine language instructions are complex!• IA-32 is a"• Complex Instruction Set Computer (CISC)!• Alternative:"• Reduced Instruction Set Computer (RISC)!8 15 Characteristics of CISC and RISC!• CISC"• Many instructions"• Many addressing modes (direct, indirect, indexed, base-pointer)"• Hardware interpretation is complex!• Few instructions required to accomplish a given job (expressive)"• Example: IA-32"• RISC"• Few instructions"• Few addressing modes (typically only direct and indirect)"• Hardware interpretation is simple!• Many instructions required to accomplish a given job (not expressive)"• Relies heavily on complier optimization"• Examples: MIPS, SPARC"16 Brief History of CISC and RISC!• Stage 1: Programmers write assembly language"• Important that assembly/machine language be expressive"• CISC dominates (esp. Intel)"• Stage 2: Programmers write high-level language"• Not important that assembly/machine language be expressive; the compiler generates it"• Important that compilers work well => assembly/machine language should be simple"• RISC takes a foothold (but CISC, esp. Intel, persists)"• Stage 3: Compilers get smarter"• Less important that assembly/machine language be simple"• Much motivation for RISC disappears"• CISC (esp. Intel) dominates the computing world"9 17 Part 2: The Assembly Process"18 The Build/Execute Process!Compiler Assembler Linker Execution myprog.c myprog.s myprog myprog.o libraries Covered in COS 320:"Compiling Techniques"Covered


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Princeton COS 217 - Assemblers and Linkers

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