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VCU EGRE 427 - Programmable ASIC Interconnect

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Chapter 7Programmable InterconnectActel Programmable InterconnectSlide 4Detail of ACT1 Channel ArchitectureElmore’s ConstantRC Delay in Antifuse ConnectionsXilinx LCA InterconnectXilinx LCA Interconnect (cont.)Xilinx Switching Matrix and Components of Interconnect DelayXilinx EPLD InterconnectAltera MAX 5000 and 7000 InterconnectAltera MAX 9000 Interconnect ArchitectureAltera FlexEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Chapter 7Programmable ASIC InterconnectApplication-Specific Integrated CircuitsMichael John Sebastian SmithAddison Wesley, 1997EGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Programmable InterconnectIn addition to programmable cells, programmable ASICs must have programmable interconnect to connect cells together for form logic functionStructure and complexity of the interconnect is determined primarily by the programming technology and architecture of the basic cellInterconnect is typically done on aluminum-based metal layersResistance of approximately 50 m/squareLine capacitance of approximately 0.2 pF/cmEarly programmable ASICs had two metal interconnect layers, but current, high density parts may have three or more metal layersEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Actel Programmable InterconnectActel interconnect is similar to a channeled gate arrayHorizontal routing channels between rows of logic modulesVertical routing channels on top of cellsEach channel has a fixed number of tracks each of which holds one wireWires in track are divided into segments of various lengths - segmented channel routingLong vertical tracks (LVT) extend the entire height of the chipEach logic module has connections to its inputs and outputs called stubsInput stubs extend vertically into routing channels above and below logic moduleOutput stub extends vertically 2 channels up and 2 channels downWires are connected by antifusesEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Actel Programmable InterconnectFigure 7.1 The interconnect architecture used in an Actel ACT family FPGA.EGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Detail of ACT1 Channel ArchitectureFigure 7.2 ACT 1 horizontal and vertical channel architecture.EGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Elmore’s ConstantFigure 7.3 Measuring the delay of a net. (a) An RC tree. (b) The waveforms as a result of closing the switch at t=0. nkkkiDitiCRetVDi1;Approximation of waveform at node i:where Rki is the resistance of the path to V0 shared by node k and node iExamples: R24 = R1, R22 = R1+R2, and R31 = R1If the switching points are assumed to be at the 0.35 and 0.65 points, the delay at node i can be approximated by DIEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997RC Delay in Antifuse ConnectionsFigure 7.4 Actel routing model. (a) A four-antifuse connection. L0 is an output stub, L1 and L3 are horizontal tracks, L2 is a long vertical track (LVT), and L4 is an output stub. (b) An RC-tree model. Each antifuse is modeled by a resistance and each interconnect segment is modeled by a capacitance.Rn - resistance of antifuse, Cn - capacitance of wire segmentD4 = R14C1 + R24C2 + R34C3 + R44C4 = (R1 + R2 + R3 + R4)C4 + (R1 + R2 + R3)C3 + (R1 + R2)C2 + R1C1If all antifuse resistances are approximately equal and much larger than the resistance of the wire segment, then: R1 = R2 = R3 = R4, and:D4 = 4RC4 + 3RC3 + 2RC2 + RC1A connection with two antifuses will generate a 3RC time constant, a connection with three antifuses will generate a 6RC time constant, and a connection with 4 antifuses will generate a 10RC time constantInterconnect delay grows quadratically ( n2) as the number of antifuses n increasesEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Xilinx LCA InterconnectXilinx LCA interconnect has a hierarchical architecture:Vertical lines and horizontal lines run between CLBsGeneral-purpose interconnect joins switch boxes (also known as magic boxes or switching matrices)Long lines run across the entire chip - can be used to form internal buses using the three-state buffers that are next to each CLBDirect connections bypass the switch matrices and directly connect adjacent CLBsProgrammable Interconnect Points (PIPs) are programmable pass transistors the connect CLB inputs and outputs to the routing networkBi-directional interconnect buffers (BIDI) restore the logic level and logic strength on long interconnect pathsEGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Xilinx LCA Interconnect (cont.)Figure 7.5 Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A simplified representation of the interconnect resources. Each of the lines is a bus.EGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Xilinx Switching Matrix and Components of Interconnect DelayFigure 7.6 Components of interconnect delay in a Xilinx LCA array. (a) A portion of the interconnect around the CLBs. (b) A switching matrix. (c) A detailed view inside the switching matrix showing the pass-transistor arrangement. (d) The equivalent circuit for the connection between nets 6 and 20 using the matrix. (e) A view of the interconnect at a Programmable Interconnection Point (PIP. (f) and (g) The equivalent schematic of a PIP connection (h) The complete RC delay path.EGRE 427 Advanced Digital DesignFigures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997Xilinx EPLD InterconnectFigure 7.7 The Xilinx EPLD UIM (Universal Interconnection


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