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VCU EGRE 427 - Design Techniques for Million Gate, High Speed FPGAs

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Design Techniques for Million Gate, High Speed FPGAsAgendaThe ProblemState-of-the-Art : 2000“Those who can not remember the past are condemned to repeat it.”State-of-the-Art : TechnologyState-of-the-Art : Gate CountState-of-the-Art : FrequencyState-of-the-Art : Clock DomainsState-of-the-Art : Computer Design HardwareState-of-the-Art : RTL LanguageState-of-the-Art : DesignState-of-the-Art : FailuresState-of-the-Art : FPGAThe Development GapSystem / SOC Design MethodologyAdjusting to a New MethodologyEffects of the Design FlowASIC versus FPGA designA Designer’s LifeHow to make a better designerPerformance Oriented Design TechniquesCoding style impactThe Keys to Language SynthesisStructuring A DesignSource Code ControlHierarchyUnderstand what the RTL does!!Serial / Priority StructureParallel StructureTri-StateBi-directional BufferRelational OperatorsAddition OperatorsResource Sharing (when it really hurts)Multiplication OperatorPipelined MultipliersA little Algebra goes a long waysD Flip-flopComplex Clock EnablesLatchesCounterState MachineSlide 44Read Only Memory (ROM)Single Port RamsDual Port RamsContent Addressable Memory (CAM)Checklist for performanceParallel GatesAttributesPhysical OptimizationFPGA High-Level FloorplannerSlide 54Slide 55Constraint Based ClusteringLogic ReplicationCritical Path RestructuringUser Applied Physical ConstraintsSlide 60Michael A. BohmMichael A. BohmChief ScientistChief ScientistTechnical Fellow Technical Fellow Mentor GraphicsMentor GraphicsDesign Techniques for Million Gate, High Speed FPGAsAgenda•The Problem•State-of-the-Art Technology•Design Issues•Performance Oriented DesignThe Problem INSPIRATIONINSPIRATIONDESIGNDESIGNSILICONSILICONPRODUCTPRODUCTHow do we move mainstream designs from ASICs to high performance FPGAs ??State-of-the-Art : 2000•Technology•Gate Count•Frequency•Clock Domains•Computer Hardware•Design Software•RTL Language•DesignFrom: “The Life of Reason”, by George Santayana, 1906“Those who can not remember thepast are condemned to repeat it.”19791978 20001980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 20004.77Mhz80864.77Mhz80886Mhz80286InterfaceManager16Mhz8038625Mhz8048650Mhz80486DX266MhzPentium200MhzPentium400MhzPentium II800MhzPentium IIIWIndows 1.0 WIndows 95 WIndows 98 WIndows 2000Technology is changing rapidly. It took 21 years to get to a 1Ghz processor. It will take 1 year to get to a 2Ghz processor.State-of-the-Art : Technology0510152025303540.5u .35u .25u .18u .15u .13u% DesignsProcess GeometriesState-of-the-Art : Gate Count05101520253035<30K 100K 300K 500K 1M 3M >3M% DesignsGate Count (excluding memory)State-of-the-Art : Frequency0510152025303566Mhz 133Mhz 266Mhz 400Mhz >400Mhz% DesignsSystem FrequencyState-of-the-Art : Clock Domains051015202530351 to 2 3 to 4 5 6 to 10 >10% DesignsState-of-the-Art : Computer Design HardwareRAM VirtualSwapEP20K160E XCV300 128MB 256MBEP20K400E XCV600 256MB 400MBEP20K600E XCV1000 512MB 800MBEP20K1000EXCV2000 1GB 1GBEP20K1500EXCV3200 1.5GB 2GBState-of-the-Art : RTL Language•Abstract Data Types•Design reusability•Compiled concepts•Design Management•Structure replicationGateLogicRTLAlgorithmSystem Verilog VHDL Vital C/C++•Abstract Data Types•Design reusability•Compiled concepts•Design Management•Structure replication•Fixed Data Types•Easier to learn•Interpreted concepts•Gate Level Sign-ofState-of-the-Art : DesignBlock DiagramTruth TableState MachineFlow Chart•Co-simulation within HDL simulator•Mix of HDL &user defined C/C++•Behavioral Synthesis•Tight physical correlation.TextState-of-the-Art : FailuresFailures %Logical 55Slow Path 13Clocking 10Power 6Race Condition 4Yield 4Misc 3IR drops 2Mixed signal interface 1FPGAs make a failure recoverable.State-of-the-Art : FPGA •APEX and Virtex at 3+ Million Gates•Maximum Operating Frequency is ~200Mhz (pushing 300Mhz)•Large blocks of memory•Imbedded Processors (PowerPC, ARM, Mips)•Copper interconnect•100K•500K•1 Million•2 Million•10 Million•1997•1998•1999•2001•3 Million•2000The Development GapDesignSizeDesignGapVerificationGap05101520253035401988 1992 1996 2000 2004Design sizeAbility to VerifyAbility to DesignAbility to FabricateSystem / SOC Design MethodologySystem / SOC Design MethodologyEmbeddedEmbeddedSoftwareSoftwareDevelopmentDevelopmentSystem Integration / ImplementationSystem Integration / ImplementationPre-existingPre-existingHardwareHardwareAlgorithmAlgorithmDevelopmentDevelopmentHardware /Hardware /SoftwareSoftwareCoverificationCoverificationHardwareHardwareDevelopmentDevelopmentRequirementsRequirementsSystem Level DesignSystem Level DesignPre-existingPre-existingSoftwareSoftwareManufacturingManufacturingAdjusting to a New MethodologyBlock1Block1‘97 - ASIC50-150K gatesMemoryMemorySystem SoftwareSystemSoftwareCPUCPUIPIPBlockABlockABlockBBlockB‘99 - SOC: 1M gatesCPUCPUCPUCPUCPUCPUIPIPIPIPIPIPIPIPIPIPIPIPBlock EBlock EBlock BBlock BASICASICBlock DBlock DBlock ABlock ABlock CBlock CMemoryMemorySystem SoftwareSystemSoftware‘02 - SOC: 10M gates•Team Design•IP Logic•More software content•Heavy with memory•Less synthesis / more chip level assemblyBehavioralBehavioralOptimizationOptimizationVHDL,VerilogVHDL,VerilogC,JavaC,JavaEfects of the Design FlowEfects of the Design FlowRTLRTLOptimizationOptimizationLogicLogicOptimizationOptimizationPhysicalPhysicalOptimizationOptimizationVHD,VerilogVHD,VerilogEDIFEDIFVHDL,VerilogVHDL,VerilogCC2:15:13:110:120:1TechnologyTechnologyOptimizationOptimizationHigher Abstraction provides more design choices !!ASIC versus FPGA design PhysicalDesignPhysicalDesignASICSynthesisASICSynthesisLogic Verif.Logic Verif.FabChipFabChipSW DebugSW DebugFabChipFabChipIterativeSystemVerificationIterativeSystemVerification$M per re-spin!!$M per re-spin!!Waiting forHardwarePrototypePhysicalDesignPhysicalDesignASIC DesignASICSynthesisASICSynthesisLogic Verif.Logic Verif.LogicDesignLogicDesignSoftware Dev.Software Dev.FPGA DesignFabChipFabChipPhysicalDesignPhysicalDesignFPGASynthesisFPGASynthesisLogic Verif.Logic Verif.SystemVerification withfewer iterationsSystemVerification withfewer iterationsSoftware Dev. and DebugSoftware Dev. and DebugRTL PrototypeRTL PrototypeLogicDesignLogicDesignA Designer’s LifeBeh / RTL DescriptionFunctional VerificationSynthesisDesign Specification8%15%Place & Route15%20% Timing ValidationSystem


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VCU EGRE 427 - Design Techniques for Million Gate, High Speed FPGAs

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