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VCU EGRE 427 - Verilog HDL

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Chapter 11Verilog HDLVerilog IdentifiersVerilog Logic Values and Data TypesVerilog Data Types (cont.)Verilog NumbersVerilog OperatorsVerilog Unary OperatorsVerilog ModulesAOI221 simulation resultsVerilog Sequential BlocksVerilog DelaysSimulation Results for AOI221 With DelaysNon Blocking AssignmentsNon Blocking Assignment Simulation ResultsVerilog ParametersVerilog Parameters (cont.)Initialization within ModulesSimulation Results for AOI221 with Initialization BlockVerilog if StatementsXor2 Simulation ResultsVerilog LoopsVerilog Case StatementsMux4 Simulation ResultsVerilog PrimitivesSimulation Results for AOI21 Using PrimitivesUser-Defined PrimitivesExample Using New PrimitiveSimulation Results for AOI321 Using PrimitivesVerilog Structural DescriptionsGates for Full AdderStructural Description of Full AdderStructural Full Adder Simulation ResultsModeling Sequential Hardware Devices in Verilog (flip-flops)DFF Simulation ResultsModeling Flip-Flops (cont.)DFF with Synchronous Preset and Clear Simulation ResultsModeling State Machines in Verilog Simple Example State DiagramExample State Machine VHDL CodeExample State Machine VHDL Code (cont.)Example State Machine Verilog CodeExample State Machine Verilog Code (cont.)State Machine Simulation Results VHDLState Machine Simulation Results VerilogState Machine Synthesis Results VHDLState Machine Synthesis Results VerilogModeling (Bi-directional) Tri-State Buffers in VerilogTri-State Buffer Simulation ResultsEGRE 427 Advanced Digital DesignChapter 11Verilog HDLApplication-Specific Integrated CircuitsMichael John Sebastian SmithAddison Wesley, 1997EGRE 427 Advanced Digital DesignVerilog HDLVerilog is an alternative hardware description language to VHDL developed by Gateway Design AutomationCadence purchased Gateway and placed Verilog in the public domain (Open Verilog International - OVI)An IEEE standard version of Verilog was developed in 1995 [IEEE Std. 1364-1995 Verilog LRM]In spite of this standardization, many flavors (usually vendor specific) of Verilog still persistVerilog syntax is much like CVerilog use is generally most prevalent on the West Coast (Silicon Valley)Most high-end commercial simulators support both VHDL and Verilog and you may receive IP blocks for your designs in Verilog which you will be expected to be able to work withOVI and VHDL International have recently merged further indicating a dual (or multi) language environment will become more prevalentEGRE 427 Advanced Digital DesignVerilog IdentifiersIdentifiers (names of variables, wires, modules, etc.) can contain any sequence of letters, numbers, ‘$’, or ‘_’The first character of an identifier must be a letter or underscoreVerilog identifiers are case sensitivereg legal_identifier, two__underscores;reg _OK, OK_, OK_$, CASE_SENSITIVE, case_sensitive;EGRE 427 Advanced Digital DesignVerilog Logic Values and Data TypesVerilog has a predefined logic-value system or value set:‘0’, ‘1’, ‘x’, and ‘z’Verilog has a limited number of data types:reg - like a variable, default value is ‘x’ and is updated immediately when on LHS of an assignmentnet - can not store values between assignments; default value is ‘z’; has subtypes:wire, trisupply1, supply0integertimeeventrealEGRE 427 Advanced Digital DesignVerilog Data Types (cont.)The default for a wire or reg is a scalarWires and reg’s may also be declared as vectors with a range of bitswire [31:0] Abus, Dbus;reg [7:0] byte;wire [31:0] Abus, Dbus;reg [7:0] byte;reg [31:0] VideoRam [7:0]; // an 8-word by 32-bit wide memoryreg [31:0] VideoRam [7:0]; // an 8-word by 32-bit wide memoryA 2-dimensional array of registers can be declared for memories - larger dimensional arrays are not allowedEGRE 427 Advanced Digital DesignVerilog NumbersConstants are written as: width’radix valueRadix is decimal (d or D), hex (h or H), octal (o or O), or binary (b or B)Constants can be declared as parameters:parameter H12_UNSIZED = ‘h 12;parameter H12_SIZED = 8`h 12;parameter D8 = 8`b 0011_1010;parameter D4 = 4`b 0xz1parameter D1 = 1`bxparameter H12_UNSIZED = ‘h 12;parameter H12_SIZED = 8`h 12;parameter D8 = 8`b 0011_1010;parameter D4 = 4`b 0xz1parameter D1 = 1`bxEGRE 427 Advanced Digital DesignVerilog Operators?: (conditional) a ternary operator|| (logical or)&& (logical and)| (bitwise or) ~| (bitwise nor)^ (bitwise xor) ^~ ~^ (bitwise xor)& (bitwise and) ~& (bitwise nand)== (logical equality) != (logical inequality) === (case equality) !== (case inequality)< (less than) <= (less than or equal) > (greater than) >= (greater than or equal)<< (shift left) >> shift right+ (addition) - (subtraction)* (multiply) / (divide) % (modulus)Unary operators: ! ~ & ~& | ~| ^ ~^ + -?: (conditional) a ternary operator|| (logical or)&& (logical and)| (bitwise or) ~| (bitwise nor)^ (bitwise xor) ^~ ~^ (bitwise xor)& (bitwise and) ~& (bitwise nand)== (logical equality) != (logical inequality) === (case equality) !== (case inequality)< (less than) <= (less than or equal) > (greater than) >= (greater than or equal)<< (shift left) >> shift right+ (addition) - (subtraction)* (multiply) / (divide) % (modulus)Unary operators: ! ~ & ~& | ~| ^ ~^ + -EGRE 427 Advanced Digital DesignVerilog Unary Operators! logical negation~ bitwise unary negation& unary reduction and~& unary reduction nand| unary reduction or~| unary reduction nor^ unary reduction xor (parity)~^ ^~ unary reduction xnor+ unary plus- unary minus! logical negation~ bitwise unary negation& unary reduction and~& unary reduction nand| unary reduction or~| unary reduction nor^ unary reduction xor (parity)~^ ^~ unary reduction xnor+ unary plus- unary minusEGRE 427 Advanced Digital DesignVerilog ModulesThe module is the basic unit of code in Verilogcorresponds to VHDL entity/architecture pairModule interfaces must be explicitly declared to interconnect modulesports must be declared as one of input, output, or inoutModules have an implicit declarative partExample also shows a continuous assignment statementmodule aoi221(A, B, C, D, E, F); output F; input A, B, C, D, E; assign F = ~((A & B) | (C & D) | E);endmodulemodule aoi221(A, B, C, D, E, F); output F; input A, B, C, D, E; assign F = ~((A & B) | (C & D) | E);endmoduleEGRE 427 Advanced Digital DesignAOI221 simulation resultsModelSim can simulate Verilog and mixed-VHDL and Verilog models as well as pure


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