VHDL Synthesis Module 60Rapid Prototyping Design ProcessModule GoalsModule OutlineSlide 5Slide 6Hardware SynthesisDefinitionsDefinitions (Cont.)Slide 10Synthesis GoalsSynthesis ConstraintsSynthesis ProcessesSynthesis CategoriesBehavioral SynthesisBehavioral Synthesis (cont.)RTL Level SynthesisLogic SynthesisSlide 19VHDL Packages for Synthesis Base TypesVHDL Packages for Synthesis Base Types (cont.)Slide 22VHDL Packages for Synthesis Arithmetic PackagesIEEE Std 1076.3 Packages Numeric_BitSlide 25Slide 26IEEE Std 1076.3 Packages Numeric_StdSlide 28TypesTypes (cont.)AttributesConcurrent Signal Assignment StatementsConditional Signal Assignment StatementsSelected Signal Assignment StatementsOperatorsOperators (cont.)Slide 37Process StatementsProcess Statements ExampleProcess Statements Incomplete Sensitivity ListSequential Signal Assignment StatementsSequential IF StatementsSequential Case StatementsSequential Loop StatementsProcedures and FunctionsProcedures and Functions (cont.)Slide 47Using Procedures and FunctionsUsing Procedures and Functions (cont.)Tri-State LogicUse of Don’t Cares (‘X’s)After ClausesInferring LatchesAvioding LatchesProblems to Avoid Inferring Latches in Complex BehaviorsProblems to Avoid Synthesizing Asynchronous State Machines!Slide 57Level Sensitive D LatchMaster-Slave D Latch (D Flip-Flop)Edge Sensitive D Flip-FlopEdge Sensitive D Flip-Flop (cont.)Edge Sensitive Flip-FlopsSlide 63Finite State Machine SynthesisMealy and Moore State Machine ModelsState Machine State EncodingState Machine Simple Example State DiagramState Machine Memory ProcessState Machine Next State ProcessState Machine Output ProcessState Machine Putting it all togetherState Machine Putting it all together (cont.)State Machine ResultsState Machines VariationsState Machines Additional State VariablesSlide 76Slide 77State Machines Additional State Variables - ResultsState Machines Combined State MachinesState Machines Combined State MachinesSlide 81State Machines Combined State Machines - ResultsSequential DatapathsSequential Datapaths Example - 8 Bit MultiplierFlow Chart for Unsigned 8 Bit Multiplier ControllerState Diagram for Unsigned 8 Bit Multiplier ControllerSlide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94Sequential Datapaths 8 Bit Multiplier - ResultsSlide 96Slide 97RTL Level Synthesis Example - A Floating Point MultiplierRTL Level Synthesis Floating Point Multiplier FunctionsRTL Level Synthesis Floating Point Multiplier Flow DiagramFloating Point Multiplier CodeSlide 102Slide 103Slide 104Slide 105Floating Point Multiplier Results - Overall SchematicFloating Point Multiplier Results - Adder SubcomponentsFloating Point Multiplier Results - Subtractor SubcomponentsFloating Point Multiplier Results - Multiplier SubcomponentFloating Point Multiplier Results - Shifter SubcomponentFloating Point Multiplier Post-Synthesis Simulation ResultsSlide 112Structural VHDLStructural VHDL And-Or-Invert ExampleSlide 115Slide 116Structural VHDL AOI ResultsSlide 118Implementation Technology ConsiderationsSlide 120SummarySummary (cont.)ReferencesCopyright  1997 RASSP E&F1VHDL SynthesisModule 60RASSP Education & Facilitation ProgramM60_01_00February 1998Copyright  1998 RASSP E&FAll rights reserved. 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You can contact us at [email protected] orhttp://rassp.scra.org/module-request/FEEDBACK/feedback-on-modules.htmlCopyright  1997 RASSP E&F2Rapid Prototyping Design ProcessVHDL SynthesisVHDL SynthesisSYSTEMDEF.FUNCTIONDESIGNH/W & S/WPART.H/WDESIGNS/WDESIGNH/WFABH/WCODEINTEG.& TESTVIRTUAL PROTOTYPERASSP DESIGN LIBRARIES AND DATABASEPrimarilysoftwarePrimarilyhardwareH/W & S/W CO-DESIGNCopyright  1997 RASSP E&F3Module GoalsIntroduce and describe levels of synthesisAlgorithmicRTL LogicPresent VHDL syntax for synthesisCombinational logic synthesisSequential logic synthesisRTL level synthesisCopyright  1997 RASSP E&F4Module OutlineSynthesis BackgroundVHDL Packages for SynthesisVHDL for Combinational Logic SynthesisTypesAttributesConcurrent signal assignment statementsOperatorsProcessesIf statementsCase statementsLoopsProcedures and functionsTri state logicUse of don’t caresAfter clausesInferring latchesProblems to avoidCopyright  1997 RASSP E&F5Module OutlineVHDL for Sequential Logic SynthesisLevel sensitive sequential logicEdge sensitive sequential logicFinite state machinesSequential datapathsVHDL for RTL Level SynthesisStructural VHDLImplementation Technology ConsiderationsSummaryCopyright  1997 RASSP E&F6Module OutlineSynthesis BackgroundVHDL Packages for SynthesisVHDL for Combinational Logic SynthesisVHDL for Sequential Logic SynthesisVHDL for RTL Level SynthesisStructural VHDLImplementation Technology Considerations SummaryCopyright  1997 RASSP E&F7Hardware SynthesisHardware Synthesis is the process of mapping an input specification for a hardware design into a hardware implementationThe input specification contains the behavioral information - what functions the final implementations is to perform,The input specification DOES NOT specify how the functions are to be performed[Parker84]Copyright  1997 RASSP E&F8DefinitionsAbstract behaviorThe operation of a digital hardware module in terms of reads and writes of variables to and from the outside world, the conditions on the reads and writes, the values of the output variables, and their partial orderingsControl-flow behaviorThe operation of a digital hardware module in terms of the loops, conditional branches, and ordering of functions performed by the moduleData pathsThe hardware which stores and performs operations on data[Parker84]Copyright  1997 RASSP E&F9Definitions (Cont.)Gate levelThe stage of hardware design at which the operations and storage elements can