LAB Assignment #3 for CMPE 650Assigned: Mon., March. 24thDue: Fri., March 28th (layout)Due: Fri, April 4th (board testing demos)Description: LAB #3: Measuring Metastable StatesPart 1: Design a two dual sided PCB (one side as ground plane) using CaptureCIS and Layout Plus.Please refer to Sections 3.11.1 and 3.11.3 of your text for a description of the experiment anddetails on the board layout (Figure 3.27). You’ll need to insert four Molex SMA edge mount con-nectors (part number 73251-1150: Digi-key: WM5534-ND) on this board for the clk, trigger, dataand Q signals, as shown in Figure 3.27. You will also need a potentiometer (BOURNS 3296X), aHex Inverting Schmitt Trigger (Fairchild semiconductor MM74HC14), a dual D-type positive-edge-triggered FFs w/ clear and preset (Texas Instruments SN74HC74N) -- I will place an orderfor these parts and update this document if additional information is needed about the footprint.You should use surface mount resistors (footprint SM/R_1206) and capacitors. Be sure to makeyour traces at least 20 mils wide (power wires can be much wider).The text indicates that the CLR (RESET) input of the FF should be connected with a delayed ver-sion of the CLK. You can implement the delay by stringing together two Schmitt triggers, andoptionally placing a capacitor between the output of the first and the input to the second to addmore delay. I would also recommend that you put a ‘jumper’ in so that you can disable the auto-matic reset operation. You’ll also want to use a jumper for the switch S1given in the book’s sche-matic.Design the longer dimension of your board horizontally and keep your board real estate as smallas possible (see the model board that I have in my office for an example).You MUST use layers TOP and GND for the top and bottom surfaces of the 2-layer board (doNOT use a routing layer and a copper pour). Be sure to set the other layers as ‘unused’ in the lay-ers spreadsheet. Note that Layout Plus shows the GND layer inverted, e.g., black is copper and redis etch (no-copper).You are allowed to have DRC errors, but only those associated with the BNC posts -- net viola-tions are NOT allowed.We will need to derive new positions for the datums before the laboratory. Please have the layoutfor your board ready at the beginning of the laboratory (4pm).longer dimensionOther suggestions and advice will be posted on my website as it becomes available.Part 2: Fabricate the board, solder on the components and carry out a hard-ware demonstration.Next friday, we will place each of your board layers into a single layout and we will fabricate theboards. You are responsible for soldering all the components and for performing the experimentsas described in the text.You will need to purchase the discrete components needed for the boards, e.g., using Digikey or alocal electronics shop, e.g., Baynesville Electronics near Towson (http://www.baynesvilleelec-tronics.com/index2.ivnu). I’ll try to get the department to buy some of these components.A lab report will be due on April 4th. Describe what you have done and show the results of yourmeasurements and calculations.Grading:50% Hardware demonstration successful.10% Proper board design/components soldered cleanly.10% Software interface using LABVIEW to collect/display data and perform calculations.30% Laboratory report description.NOTES on Capture CIS and Layout Plus: (I’ll update this as info becomes available).You’ll need to move the ‘datum’ once you’ve finished the layout but before you’ve written theGERBER files. It’s under Tools/Dimension/Move Datum. We’ll need to make sure everyone’sdesign has a different reference point so we can combine them together using ViewMate. Laststep is to write the Gerber files, use Auto/Run PostProcessor.To force thermal reliefs:Tools->Footprint->Force Thermal relief (for all nets or one net at time).To set size:Options->Thermal Relief Settings (and make sure you spoke width is at least