Digital Systems PCB Layer Stacking CMPE 6501 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Layer Stack GuidelinesLayer stack defines:• The ordering of the signal, power and GND layers• The dielectric constant of the substrate• The spacing between layers• Optionally, the trace dimensions and minimum spacing.Bear in mind, unlike VLSI, the greater the wiring density, the greater the pro-duction costs per square inch.Start by designing the power and GND layers first.This requires knowledge of signal rise times, the # of signals, the boarddimensions and a guess on the trace width.Estimate the self-inductance and mutual inductance using solid, hatched andfingers GND plane models.• Fingers model: all traces interact.• Hatched model: parallel traces interact.• Plane model: only adjacent traces interact.Digital Systems PCB Layer Stacking CMPE 6502 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Layer Stack GuidelinesTry to use power and GND planes in pairs.Single planes offset to one side or the other can cause warping.Power planes can be used as low-inductance signal-current paths (just likeGND planes) assuming adequate by-pass capacitors are installed.In this case, transmission lines work as well as they do over a GNDplane.Transmission striplines routed between one power and GND layer ortwo power layers also work.A Chassis Layer may be needed for driving signals off the board, otherwiseexternal radiation will cause FCC problems.Start by choosing a low-speed or controlled rise time driver.Connecting the driver to the ordinary digital logic ground on board isprobably not a good idea.Digital Systems PCB Layer Stacking CMPE 6503 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Chassis LayerConsider the following:Digital logic GNDs (on board) are notorious for high-frequency noise voltages.These GNDs carry many returning currents acting across their self-inductance.The high-frequency fluctuations are too small to cause trouble for digitallogic on board.However, the driver acts to broadcast the ground noise outside the cabi-net, and the level will almost always exceed FCC limits.+-VdriveTrue Earth GND+-Vlogic+-Vout = Vdrive + VlogicOutput signalDigital Systems PCB Layer Stacking CMPE 6504 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Chassis LayerOne solution is to add a chassis plane adjacent to the GND plane on the board.This provides a high level of capacitance coupling between the planes.The chassis layer is then screwed, soldered or welded to the external chassisalong one continuous axis near the controlled rise-time driver.This effectively shorts the digital GND plane to the chassis.Ordinary capacitors will not function as a short between the digital logicGND and the chassis GND (lead inductance is too high).The separate plane approach ensure the electrical separation of these twoGNDs.If separation is not important, short the digital GND directly to the chassis(no separate chassis GND plane is needed).Digital Systems PCB Layer Stacking CMPE 6505 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Selecting Trace DimensionsSince board cost is proportional to the number of layers and its surface area,we tend to squeeze traces tightly together.This increases crosstalk and reduces routing area available for power/GND.Therefore, crosstalk, routing density and power are traded off to reduce cost.The power-handling capacity of a PCB trace depends on its cross-sectional areaand allowable temperature increase (typically 10 degrees).1001010.110-610-510-410-310-25Temperaturerise(degrees C)102040100RMS current(A)Cross-sectional area of trace (in.2)0.010 in. wide1-oz copper (0.00135)1.35 X 10-5 in.2750 mA maxDigital Systems PCB Layer Stacking CMPE 6506 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Selecting Trace DimensionsPower is rarely a serious constraint except for large power buses.However, as thin-film technology becomes more widely available, thismay become an issue.Other than power, manufacturing tolerances also lower bound trace width.Most designers won’t use the min-width since yield goes down (cost up).Also, line width variations and variations in the electrical permittivity of the sub-strate make it difficult to keep impedance within tolerance at min widths.Trace width: Set by power, cost (yield) and impedance constraints.Trace height: Set by impedance once trace width is established.Process Min line width (in.)Gold screened onto thick film substrate 0.010Etched copper on epoxy board with plating 0.004Etched copper on epoxy board with no plating 0.003Gold evaporated onto thin film substrate and etched 0.001Digital Systems PCB Layer Stacking CMPE 6507 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Selecting Trace DimensionsTrace spacing is determined using our crosstalk formula:Trace spacing is measured center-to-center and is called trace pitch.The unused space between traces is called trace separation.Therefore, trace width + trace separation = trace pitch.Of course, using more layers allows larger pitches but higher cost.So a trade-off between cost and crosstalk determines acceptable pitch.The optimization problem is "route N connections of average wire length Xusing M layers".Average wire length can be approximated from Rent’s rule."Half the wires in a quadrant cross the quadrant boundary."CrosstalkK1 D H⁄( )2+------------------------------=Digital Systems PCB Layer Stacking CMPE 6508 (4/15/08)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Selecting Trace DimensionsFrom this, we can estimate the average pitch to route N connections:Here, N is assumed distributed according to Rent’s rule, X and Y are thedimensions of the board (in.), and M is the # of board layers.For example, an 8X12 in. board having 800 connections routed on 4 layersyields a trace pitch of 0.132 in.If the board has a lot of DIP through-holes, this requires traces to be runbetween the pins.On average, no more than half of the space between pins can be filled.However, for through-hole boards, the average pitch (above eq) and the mini-mum pitch (from crosstalk considerations) can be very different.For surface mount boards, the average pitch and the minimum pitch may besimilar for the inner layers.paveXYN------------2.7M=Digital Systems PCB Layer Stacking CMPE 6509 (4/15/08)UMBCU M B CUNIVERSITY OF