Digital Systems Clock Distribution II CMPE 6501 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Differential DistributionDifferential clocks are more robust to noisy environments than single-endedclocks for 2 reasons:• Signal swing is twice that of single-ended.Therefore, they can tolerate twice the interference• Any common mode noise is cancelled out completely in the receiver.Crosstalk problems are particularly acute in TTL systems that use an ECLclock distribution.The low skew characteristics of an ECL system make it attractive.However, the ECL signals are low in amplitude, and the larger TTL signalseasily generate interfering crosstalk at the ECL receivers.Making the ECL clock distribution differential helps overcome commonmode noise problems created by this type of crosstalk.Digital Systems Clock Distribution II CMPE 6502 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Differential DistributionBear in mind that this strategy does not help with "single-sided" crosstalk,i.e., crosstalk created by one clock wire and a signal wire running too closeto one another.Differential signaling helps a lot with communications between boards.The difference in the noise voltage on the GND planes of the two sys-tems cancel in the differential receiver.Clock Duty Cycle:The ideal duty cycle for a clock signal is 50%.The falling edge precisely bisects the signal changes in data wires.The average DC value of an ideal clock lies halfway between the HI and LOstates.The property allows for the design of a simple feedback mechanismdesigned to keep the duty cycle fixed at 50%.Digital Systems Clock Distribution II CMPE 6503 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Clock Signal Duty CycleThe asymmetric nature of rising/falling wfms of clock repeaters is the reasonwhy clocks drift away (become unbalanced) form the 50% duty cycle.All gates have asymmetric response with regard to their rising and fall-ing edges.A pulse that propagates through a gate is either shortened (pulse widthcompression) or lengthened (pulse width expansion).As a chain of gates gets longer, the level of pulse width distortion adds.For example, assume the input pulse is positive-going and assume thedelay of the rising edge exceeds the delay of the falling edge.The succession of positive pulses will become increasing shorter, andeventually disappear for long strings of buffers.Digital Systems Clock Distribution II CMPE 6504 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Clock Signal Duty CycleTwo tricks can be used to solve this problem.• Invert the clock signal at every stage in an inverting chain.This converts rising edges to falling ones and cancels pulse width com-pression in adjacent stages, over that of a non-inverting chain.• Use an analog circuit that tracks the average DC value.This only works with logic that has symmetric switching thresholds.OUT1K0.047INVBBVEEC2input thresholdadjusted by C2Digital Systems Clock Distribution II CMPE 6505 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Clock Signal Duty CycleThis circuit computes the average DC value and stores it on C2.The value on C2adjusts the input switching threshold to achieve an outputduty cycle closer to 50%.Canceling Parasitic Capacitance of Clock RepeatersAdding a device to the clock wire adds parasitic capacitance, whichshifts the received clock phase on all devices on the line.This circuit can be used to combat the parasitic capacitance.parasiticcapacitanceR1R2100K100KVCCC1L1Clock inputof circuit trace,connector andgate.CpDigital Systems Clock Distribution II CMPE 6506 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Canceling Parasitic Capacitance of Clock RepeatersThe inductor presents a negative reactance at the clock frequency and par-tially cancels the parasitic capacitance of the clk receiver circuit.This is called a matching network.Note the inductor-cancellation trick works only at the fundamental fre-quency, higher harmonics get no relief.Be sure to use a clk driver with slow rise and fall times.Such clks have lower harmonic content (more sinusoidal-like) and theneutralizing effect works better.The two resistors are optional.However, when used in a hot plugging environment, if they are absent, then asurge of current to charge C1 will distort the clock signal.A properly designed hot plug card receives power before touching the clockbus, and therefore, the resistors, if present, provide the charging current.Digital Systems Clock Distribution II CMPE 6507 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Canceling Parasitic Capacitance of Clock RepeatersKeeping C1 small helps shorten the precharge time.The minimum value for C1 is about 100 times Cp.With R1 and R2 present, the precharge time to bring C1 within 1% of its finalvalue, (HI+LO)/2, is given as:Decoupling Clock Receivers from the Clock BusClock taps on the clk bus can seriously distort the clk wfm.Occurs when there are lots of taps, when the taps have large cap or whenoperating at high speed.C1100Cp=L112πf( )2C1------------------------12πf( )2Cp-------------------------+=tpc4.6R1R2R1R2+-------------------C1=Digital Systems Clock Distribution II CMPE 6508 (5/1/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Decoupling Clock Receivers from the Clock BusOne way to reduce the impact is to build a 3:1 attenuator at the input to eachclock gate (receiver).This will require more voltage gain in each clk receiver.The attenuation network is inserted in series with clk receiver, at an imped-ance that is twice that of the receiver at the clock frequency.This effectively triples the apparent input impedance of the receiver.It also reduces the voltage to be interpreted by the receiver, but mostgates have a lot of excess voltage gain.Differential receiver circuits are commonly used here, which have plenty ofgain and a precisely controlled input-switching