Digital Systems Power Systems II CMPE 6501 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Capacitance of PWR and GND PlanesParallel PWR and GND planes provide a third level of bypass capacitance andhas no lead inductance and no ESR.It helps to reduce power and ground noise at very high frequencies.The capacitance is given by:For FR-4, PWR and GND plane capacitance for planes separated by 0.01 in. is100pF/in2.Cpower plane0.225εrAd-----------------------=εr = relative permeability of FR-4 (4.5)A and d are the area and separation.1001010.10.01106105109107108C2 (10uF, 0.1Ω)Wiring inductanceC3 (32-0.016uF, 0.1Ω)ImpedanceMagnitude (Ω)PWR/GND plane capAggregate responseis parallel combo of all 4Digital Systems Power Systems II CMPE 6502 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Capacitance of PWR and GND PlanesThe analysis that Joy did for the 2003 ITC paper on the probe card and chippower grid:Note that both of these impedance profile plots include the effect of parasiticseries resistance of the capacitors called equivalent series resistance or ESR.ΩPower supplyZtarget = 6.25mΩPower supply fails1st stage1st+2nd stageto meet targetC4modelOn-chipdecouplefrequency (Hz)Digital Systems Power Systems II CMPE 6503 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Test Gig for Measuring Step Response of Power Distribution SystemThis setup applies a small current step to the power system and observes thereaction.The output impedance of this arrangement is 25 Ω (parallel of 50 Ω frompulse and scope).Set rise time from pulse generator to rise time expected in system and set out-put step size to 5 V.This gives an output current step of 5 V/25 Ω = 0.2 A.So scale the measured response by ∆I/0.2 to obtain response for ∆I.Pulsegenerator+-V(t)50ΩScope+-50ΩterminationProbe the powersystem using this wireSet for 100-kHz sqr waveConnect to GNDof PWR systemwith the power turned onDigital Systems Power Systems II CMPE 6504 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Choosing a Bypass CapacitorCapacitors are not perfect -- each has• Lead inductance• Package inductance• Mounting inductance• Equivalent series resistance (ESR)• A dielectric that has significant temperature sensitivity• A voltage limit over which it "blows out" or shorts outThe ESR is a real-valued impedance (not imaginary like inductance) and is nota strong function of frequency.Both lead inductance and ESR act in series with the capacitor, degrading itseffectiveness as a bypass element.The impedance magnitude, X(f), is given by:X f( ) ESR21–2πfC------------- 2πfL+  2+=Digital Systems Power Systems II CMPE 6505 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Choosing a Bypass CapacitorThe resonance peak at ~300 MHz is caused by the lead inductance of thecapacitor array and the capacitance between PWR and GND planes.This is not an issue if Fknee is down around 100 MHz.If it is higher, a surface-mounted capacitor array raises the resonance frequencyand reduces its amplitude.ESR does not always appear on the manufacturer’s data sheet but it isextremely important.1001010.10.01106105109107108C2 (10uF, 0.1Ω)Wiring inductanceC3 (32-0.016uF, 0.1Ω)ImpedanceMagnitude (Ω)PWR/GND plane capAggregate responseis parallel combo of all 4Digital Systems Power Systems II CMPE 6506 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Choosing a Bypass CapacitorThe lead inductance and ESR effect an RC circuit when the R is low.It quickens the rise time.The spike results from the lead inductance.The area under the spike can be used to compute the inductance.Immediately following the spike, the wfm is flat and offset from 0.This is caused by the ESR (capacitor has not yet begun to charge).time (ns)mVspikestepslow rampLRSA∆V-----------=RS is src resistance of test jig∆V is open circuit step voltage of test jigESRRSX∆V X–------------------=X is measured step voltage after spikeDigital Systems Power Systems II CMPE 6507 (4/24/07)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Choosing a Bypass CapacitorHere, a good model is the capacitor is the ESR tied directly to ground.The source impedance in series with the ESR forms a resistor divider.The voltage fraction from previous equation X the source resistanceyields the ESR.The effect of the capacitor charging is given by the ramp.dV/dt is equal to the charging current divided by the capacitance.The charging current is equal roughly to the test circuit open-circuit volt-age (∆V) divided by the source resistance.Bear in mind that the spike includes the effect of the lead inductance and ESR.Remember to subtract out the ESR before measuring the area.C∆V X–RSdV dt⁄(