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UT EE 345M - Programming manual

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1 About this document1.1 Typographical conventions1.2 List of abbreviations for registers1.3 About the STM32 Cortex-M3 processor and core peripheralsFigure 1. STM32 Cortex-M3 implementation1.3.1 System level interface1.3.2 Integrated configurable debug1.3.3 Cortex-M3 processor features and benefits summary1.3.4 Cortex-M3 core peripherals2 The Cortex-M3 processor2.1 Programmers model2.1.1 Processor mode and privilege levels for software execution2.1.2 StacksTable 1. Summary of processor mode, execution privilege level, and stack use options2.1.3 Core registersFigure 2. Processor core registersTable 2. Core register set summary (continued)Figure 3. APSR, IPSR and EPSR bit assignmentsFigure 4. PSR bit assignmentsTable 3. PSR register combinationsTable 4. APSR bit definitionsTable 5. IPSR bit definitionsTable 6. EPSR bit definitionsFigure 5. PRIMASK bit assignmentsTable 7. PRIMASK register bit definitionsFigure 6. FAULTMASK bit assignmentsTable 8. FAULTMASK register bit definitionsFigure 7. BASEPRI bit assignmentsTable 9. BASEPRI register bit assignmentsFigure 8. CONTROL bit assignmentsTable 10. CONTROL register bit definitions (continued)2.1.4 Exceptions and interrupts2.1.5 Data types2.1.6 The Cortex microcontroller software interface standard (CMSIS)2.2 Memory modelFigure 9. Memory map2.2.1 Memory regions, types and attributes2.2.2 Memory system ordering of memory accessesTable 11. Ordering of memory accesses2.2.3 Behavior of memory accessesTable 12. Memory access behavior (continued)2.2.4 Software ordering of memory accesses2.2.5 Bit-bandingTable 13. SRAM memory bit-banding regionsTable 14. Peripheral memory bit-banding regionsFigure 10. Bit-band mapping2.2.6 Memory endiannessFigure 11. Little-endian example2.2.7 Synchronization primitives2.2.8 Programming hints for the synchronization primitivesTable 15. C compiler intrinsic functions for exclusive access instructions2.3 Exception model2.3.1 Exception statesNote: An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state.2.3.2 Exception typesTable 16. Properties of the different exception types (continued)2.3.3 Exception handlers2.3.4 Vector tableFigure 12. Vector table2.3.5 Exception priorities2.3.6 Interrupt priority grouping2.3.7 Exception entry and returnTable 17. Exception return behavior (continued)2.4 Fault handling2.4.1 Fault typesTable 18. Faults (continued)2.4.2 Fault escalation and hard faults2.4.3 Fault status registers and fault address registersTable 19. Fault status and fault address registers2.4.4 Lockup2.5 Power management2.5.1 Entering sleep mode2.5.2 Wakeup from sleep mode2.5.3 The external event input2.5.4 Power management programming hints3 The Cortex-M3 instruction set3.1 Instruction set summaryTable 20. Cortex-M3 instructions (continued)3.2 Intrinsic functionsTable 21. CMSIS intrinsic functions to generate some Cortex-M3 instructionsTable 22. CMSIS intrinsic functions to access the special registers3.3 About the instruction descriptions3.3.1 Operands3.3.2 Restrictions when using PC or SP3.3.3 Flexible second operand3.3.4 Shift operationsFigure 13. ASR#3Figure 14. LSR#3Figure 15. LSL#3Figure 16. ROR #3Figure 17. RRX #33.3.5 Address alignment3.3.6 PC-relative expressions3.3.7 Conditional executionTable 23. Condition code suffixes3.3.8 Instruction width selection3.4 Memory access instructionsTable 24. Memory access instructions3.4.1 ADR3.4.2 LDR and STR, immediate offsetTable 25. Immediate, pre-indexed and post-indexed offset ranges3.4.3 LDR and STR, register offset3.4.4 LDR and STR, unprivileged3.4.5 LDR, PC-relativeTable 26. label-PC offset ranges3.4.6 LDM and STM3.4.7 PUSH and POP3.4.8 LDREX and STREX3.4.9 CLREX3.5 General data processing instructionsTable 27. Data processing instructions3.5.1 ADD, ADC, SUB, SBC, and RSB3.5.2 AND, ORR, EOR, BIC, and ORN3.5.3 ASR, LSL, LSR, ROR, and RRX3.5.4 CLZ3.5.5 CMP and CMN3.5.6 MOV and MVN3.5.7 MOVT3.5.8 REV, REV16, REVSH, and RBIT3.5.9 TST and TEQ3.6 Multiply and divide instructionsTable 28. Multiply and divide instructions3.6.1 MUL, MLA, and MLS3.6.2 UMULL, UMLAL, SMULL, and SMLAL3.6.3 SDIV and UDIV3.7 Saturating instructions3.7.1 SSAT and USAT3.8 Bitfield instructionsTable 29. Packing and unpacking instructions3.8.1 BFC and BFI3.8.2 SBFX and UBFX3.8.3 SXT and UXT3.8.4 Branch and control instructionsTable 30. Branch and control instructions3.8.5 B, BL, BX, and BLXTable 31. Branch ranges3.8.6 CBZ and CBNZ3.8.7 IT3.8.8 TBB and TBH3.9 Miscellaneous instructionsTable 32. Miscellaneous instructions (continued)3.9.1 BKPT3.9.2 CPS3.9.3 DMB3.9.4 DSB3.9.5 ISB3.9.6 MRS3.9.7 MSR3.9.8 NOP3.9.9 SEV3.9.10 SVC3.9.11 WFE3.9.12 WFI4 Core peripherals4.1 About the STM32 core peripheralsTable 33. STM32 core peripheral register regions4.2 Memory protection unit (MPU)Table 34. Memory attributes summary4.2.1 MPU access permission attributesTable 35. TEX, C, B, and S encodingTable 36. Cache policy for memory attribute encodingTable 37. AP encoding (continued)4.2.2 MPU mismatch4.2.3 Updating an MPU regionFigure 18. Subregion example4.2.4 MPU design hints and tipsTable 38. Memory region attributes for STM324.2.5 MPU type register (MPU_TYPER)4.2.6 MPU control register (MPU_CR)Note: When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.If the MPU is disabled, the processor ignores this bit.Note: When the MPU is disabled, if this bit is set to 1 the behavior is unpredictable.4.2.7 MPU region number register (MPU_RNR)4.2.8 MPU region base address register (MPU_RBAR)4.2.9 MPU region attribute and size register (MPU_RASR)Table 39. Example SIZE field valuesTable 40. MPU register map and reset values (continued)4.3 Nested vectored interrupt controller (NVIC)4.3.1 The CMSIS mapping of the Cortex-M3 NVIC registersTable 41. Mapping of interrupts to the interrupt variables4.3.2 Interrupt set-enable registers (NVIC_ISERx)4.3.3 Interrupt clear-enable registers (NVIC_ICERx)4.3.4 Interrupt set-pending registers (NVIC_ISPRx)4.3.5 Interrupt clear-pending registers (NVIC_ICPRx)4.3.6 Interrupt active bit registers (NVIC_IABRx)4.3.7 Interrupt priority registers (NVIC_IPRx)Figure 19. NVIC__IPRx register mappingTable 42. IPR bit assignments4.3.8 Software trigger interrupt register (NVIC_STIR)4.3.9 Level-sensitive and pulse interrupts4.3.10 NVIC design hints and tipsTable 43. CMSIS functions for NVIC control (continued)4.3.11 NVIC register mapTable 44.


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UT EE 345M - Programming manual

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