PM0056 Programming manual STM32F10xxx Cortex M3 programming manual This programming manual provides information for application and system level software developers It gives a full description of the STM32F10xxx Cortex M3 processor programming model instruction set and core peripherals The STM32F10xxx Cortex M3 processor is a high performance 32 bit processor designed for the microcontroller market It offers significant benefits to developers including April 2010 Outstanding processing performance combined with fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Efficient processor core system and memories Ultra low power consumption with integrated sleep modes Platform security Doc ID 15491 Rev 3 1 154 www st com Contents PM0056 Contents 1 2 About this document 10 1 1 Typographical conventions 10 1 2 List of abbreviations for registers 10 1 3 About the STM32 Cortex M3 processor and core peripherals 10 System level interface 11 1 3 2 Integrated configurable debug 11 1 3 3 Cortex M3 processor features and benefits summary 12 1 3 4 Cortex M3 core peripherals 13 The Cortex M3 processor 14 2 1 2 2 2 3 2 154 1 3 1 Programmers model 14 2 1 1 Processor mode and privilege levels for software execution 14 2 1 2 Stacks 14 2 1 3 Core registers 15 2 1 4 Exceptions and interrupts 23 2 1 5 Data types 23 2 1 6 The Cortex microcontroller software interface standard CMSIS 24 Memory model 25 2 2 1 Memory regions types and attributes 26 2 2 2 Memory system ordering of memory accesses 27 2 2 3 Behavior of memory accesses 27 2 2 4 Software ordering of memory accesses 28 2 2 5 Bit banding 29 2 2 6 Memory endianness 31 2 2 7 Synchronization primitives 32 2 2 8 Programming hints for the synchronization primitives 33 Exception model 34 2 3 1 Exception states 34 2 3 2 Exception types 34 2 3 3 Exception handlers 36 2 3 4 Vector table 37 2 3 5 Exception priorities 37 2 3 6 Interrupt priority grouping 38 2 3 7 Exception entry and return 38 Doc ID 15491 Rev 3 PM0056 Contents 2 4 2 5 3 Fault handling 41 2 4 1 Fault types 41 2 4 2 Fault escalation and hard faults 42 2 4 3 Fault status registers and fault address registers 43 2 4 4 Lockup 43 Power management 43 2 5 1 Entering sleep mode 44 2 5 2 Wakeup from sleep mode 44 2 5 3 The external event input 45 2 5 4 Power management programming hints 45 The Cortex M3 instruction set 46 3 1 Instruction set summary 46 3 2 Intrinsic functions 51 3 3 About the instruction descriptions 52 3 4 3 5 3 3 1 Operands 52 3 3 2 Restrictions when using PC or SP 53 3 3 3 Flexible second operand 53 3 3 4 Shift operations 54 3 3 5 Address alignment 57 3 3 6 PC relative expressions 57 3 3 7 Conditional execution 58 3 3 8 Instruction width selection 60 Memory access instructions 61 3 4 1 ADR 61 3 4 2 LDR and STR immediate offset 62 3 4 3 LDR and STR register offset 64 3 4 4 LDR and STR unprivileged 65 3 4 5 LDR PC relative 66 3 4 6 LDM and STM 68 3 4 7 PUSH and POP 69 3 4 8 LDREX and STREX 71 3 4 9 CLREX 72 General data processing instructions 73 3 5 1 ADD ADC SUB SBC and RSB 74 3 5 2 AND ORR EOR BIC and ORN 76 Doc ID 15491 Rev 3 3 154 Contents PM0056 3 6 3 7 3 5 3 ASR LSL LSR ROR and RRX 77 3 5 4 CLZ 78 3 5 5 CMP and CMN 79 3 5 6 MOV and MVN 80 3 5 7 MOVT 81 3 5 8 REV REV16 REVSH and RBIT 82 3 5 9 TST and TEQ 83 Multiply and divide instructions 84 3 6 1 MUL MLA and MLS 84 3 6 2 UMULL UMLAL SMULL and SMLAL 86 3 6 3 SDIV and UDIV 87 Saturating instructions 88 3 7 1 3 8 3 9 4 4 154 SSAT and USAT 88 Bitfield instructions 89 3 8 1 BFC and BFI 90 3 8 2 SBFX and UBFX 90 3 8 3 SXT and UXT 91 3 8 4 Branch and control instructions 92 3 8 5 B BL BX and BLX 93 3 8 6 CBZ and CBNZ 94 3 8 7 IT 95 3 8 8 TBB and TBH 97 Miscellaneous instructions 98 3 9 1 BKPT 99 3 9 2 CPS 99 3 9 3 DMB 100 3 9 4 DSB 100 3 9 5 ISB 101 3 9 6 MRS 101 3 9 7 MSR 102 3 9 8 NOP 103 3 9 9 SEV 103 3 9 10 SVC 104 3 9 11 WFE 104 3 9 12 WFI 105 Core peripherals 106 Doc ID 15491 Rev 3 PM0056 Contents 4 1 About the STM32 core peripherals 106 4 2 Memory protection unit MPU 106 4 3 4 4 4 2 1 MPU access permission attributes 107 4 2 2 MPU mismatch 109 4 2 3 Updating an MPU region 109 4 2 4 MPU design hints and tips 111 4 2 5 MPU type register MPU TYPER 112 4 2 6 MPU control register MPU CR 113 4 2 7 MPU region number register MPU RNR 114 4 2 8 MPU region base address register MPU RBAR 115 4 2 9 MPU region attribute and size register MPU RASR 117 Nested vectored interrupt controller NVIC 119 4 3 1 The CMSIS mapping of the Cortex M3 NVIC registers 120 4 3 2 Interrupt set enable registers NVIC ISERx 121 4 3 3 Interrupt clear enable registers NVIC ICERx 122 4 3 4 Interrupt set pending registers NVIC ISPRx 123 4 3 5 Interrupt clear pending registers NVIC ICPRx 124 4 3 6 Interrupt active bit registers NVIC IABRx 125 4 3 7 Interrupt priority registers NVIC IPRx 126 4 3 8 Software trigger interrupt register NVIC STIR 127 4 3 9 Level sensitive and pulse interrupts 127 4 3 10 NVIC design hints and tips 128 4 3 11 NVIC register map 129 System control block SCB 130 4 4 1 CPUID base register SCB CPUID 130 4 4 2 Interrupt control and state register SCB ICSR 131 4 4 3 Vector table offset register SCB VTOR 133 4 4 4 Application interrupt and reset control register SCB AIRCR 134 4 4 5 System control register SCB SCR 135 4 4 6 Configuration and control register SCB CCR 136 4 4 7 System handler priority registers SHPRx 137 4 4 8 System handler control and state register SCB SHCSR 139 4 4 9 Configurable fault status register SCB CFSR 141 4 4 10 Hard fault status register SCB HFSR 144 4 4 11 Memory management fault address register SCB MMFAR 146 4 4 12 Bus fault address register SCB BFAR 146 4 4 13 System control block design hints and …
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