The ARM Instruction Set ArchitectureMain features of the ARM Instruction SetCoprocessorsThumbProcessor ModesThe RegistersThe ARM Register SetRegister Organization SummaryAccessing Registers using ARM InstructionsThe Program Status Registers (CPSR and SPSRs)Condition FlagsThe Program Counter (R15)Exception Handling and the Vector TableThe Original Instruction PipelinePipeline changes for ARM9TDMIPipeline changes for ARM10 vs. ARM11 PipelinesARM Instruction Set FormatConditional ExecutionThe Condition FieldUsing and updating the Condition FieldConditional Execution and FlagsBranch instructions (1)Branch instructions (2)Branch instructions (3)Conditional BranchesData processing InstructionsArithmetic OperationsComparisonsLogical OperationsData MovementThe Barrel ShifterBarrel Shifter - Left ShiftBarrel Shifter - Right ShiftsBarrel Shifter - Rotations Using the Barrel Shifter: The Second OperandSecond Operand : Shifted RegisterSecond Operand: Using a Shifted RegisterSecond Operand: Immediate Value (1)Second Operand: Immediate Value (2)Loading full 32 bit constantsMultiplication InstructionsMultiplication ImplementationExtended Multiply InstructionsMultiply-Long & Multiply-Accumulate LongLoad / Store InstructionsSingle register data transferLoad and Store Word or Byte: Base RegisterLoad/Store Word or Byte: Offsets from the Base RegisterLoad/Store Word or Byte: Pre-indexed AddressingLoad and Store Word or Byte: Post-indexed AddressingLoad and Stores with User Mode PrivilegeExample Usage of Addressing ModesOffsets for Halfword and Signed Halfword / Byte AccessEffect of endianessYA Endianess ExampleBlock Data Transfer (1)Block Data Transfer (2)StacksStack OperationStack ExamplesStacks and SubroutinesDirect functionality of Block Data TransferExample: Block CopySwap and Swap Byte InstructionsSoftware Interrupt (SWI)BackupAssembler: Pseudo-opsAssembler: Pseudo-opsAssembler: Pseudo-opsAssembly Line FormatExample: C assignmentsExample: C assignmentExample: C assignmentExample: if statementif statement, cont’d.if statement, cont’d.Example: Conditional instruction implementationConditional instruction implementation, cont’d.Example: switch statementExample: FIR filterFIR filter, cont’.dARM Instruction Set Summary (1/4)ARM Instruction Set Summary (2/4)ARM Instruction Set Summary (3/4)ARM Instruction Set Summary (4/4)EE382N-4 Embedded Systems ArchitectureThe ARM Instruction Set ArchitectureMark McDermottWith help from our good friends at ARMFall 20088/22/2008EE382N-4 Embedded Systems ArchitectureMain features of the ARM Instruction Set All instructions are 32 bits long. Most instructions execute in a single cycle. Most instructions can be conditionally executed. A load/store architecture – Data processing instructions act only on registers• Three operand format• Combined ALU and shifter for high speed bit manipulation– Specific memory access instructions with powerful auto‐indexing addressing modes.• 32 bit and 8 bit data types– and also 16 bit data types on ARM Architecture v4.• Flexible multiple register load and store instructions Instruction set extension via coprocessors Very dense 16‐bit compressed instruction set (Thumb)28/22/2008EE382N-4 Embedded Systems ArchitectureCoprocessors3– Up to 16 coprocessors can be defined– Expands the ARM instruction set– Each coprocessor can have up to 16 private registers of any reasonable size– Load‐store architectureEE382N-4 Embedded Systems ArchitectureThumb Thumb is a 16‐bit instruction set– Optimized for code density from C code– Improved performance form narrow memory– Subset of the functionality of the ARM instruction set Core has two execution states –ARM and Thumb– Switch between them using BX instruction Thumb has characteristic features:– Most Thumb instruction are executed unconditionally– Many Thumb data process instruction use a 2‐address format– Thumb instruction formats are less regular than ARM instruction formats, as a result of the dense encoding.4EE382N-4 Embedded Systems ArchitectureProcessor Modes The ARM has six operating modes:– User (unprivileged mode under which most tasks run)– FIQ (entered when a high priority (fast) interrupt is raised)– IRQ (entered when a low priority (normal) interrupt is raised)– Supervisor (entered on reset and when a Software Interrupt instruction is executed)– Abort (used to handle memory access violations)– Undef (used to handle undefined instructions) ARM Architecture Version 4 adds a seventh mode:– System (privileged mode using the same registers as user mode)58/22/2008EE382N-4 Embedded Systems ArchitectureThe Registers ARM has 37 registers in total, all of which are 32‐bits long.– 1 dedicated program counter– 1 dedicated current program status register– 5 dedicated saved program status registers– 30 general purpose registers However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access – a particular set of r0‐r12 registers– a particular r13 (the stack pointer) and r14 (link register)– r15 (the program counter)– cpsr (the current program status register) And privileged modes can also access– a particular spsr (saved program status register)68/22/2008EE382N-4 Embedded Systems Architecturer0r1r2r3r4r5r6r7r8r9r10r11r12r13 (sp)r14 (lr)r15 (pc)cpsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr8r9r10r11r12r13 (sp)r14 (lr)spsrFIQ IRQ SVC Undef AbortUser Moder0r1r2r3r4r5r6r7r8r9r10r11r12r13 (sp)r14 (lr)r15 (pc)cpsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr8r9r10r11r12r13 (sp)r14 (lr)spsrCurrent Visible RegistersBanked out RegistersFIQ IRQ SVC Undef Abortr0r1r2r3r4r5r6r7r15 (pc)cpsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr8r9r10r11r12r13 (sp)r14 (lr)spsrCurrent Visible RegistersBanked out RegistersUser IRQ SVC Undef Abortr8r9r10r11r12r13 (sp)r14 (lr)FIQ ModeIRQ Moder0r1r2r3r4r5r6r7r8r9r10r11r12r15 (pc)cpsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr8r9r10r11r12r13 (sp)r14 (lr)spsrCurrent Visible RegistersBanked out RegistersUser FIQ SVC Undef Abortr13 (sp)r14 (lr)Undef Moder0r1r2r3r4r5r6r7r8r9r10r11r12r15 (pc)cpsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr13 (sp)r14 (lr)spsrr8r9r10r11r12r13 (sp)r14 (lr)spsrCurrent Visible