EE382N 4 Embedded Systems Architecture The ARM Instruction Set Architecture Mark McDermott With help from our good friends at ARM Fall 2008 8 22 2008 EE382N 4 Embedded Systems Architecture Main features of the ARM Instruction Set All instructions are 32 bits long Most instructions execute in a single cycle Most instructions can be conditionally executed A load store architecture Data processing instructions act only on registers Three operand format Combined ALU and shifter for high speed bit manipulation Specific memory access instructions with powerful auto indexing addressing modes 32 bit and 8 bit data types and also 16 bit data types on ARM Architecture v4 Flexible multiple register load and store instructions Instruction set extension via coprocessors Very dense 16 bit compressed instruction set Thumb 8 22 2008 2 EE382N 4 Embedded Systems Architecture Coprocessors Up to 16 coprocessors can be defined Expands the ARM instruction set Each coprocessor can have up to 16 private registers of any reasonable size Load store architecture 3 EE382N 4 Embedded Systems Architecture Thumb Thumb is a 16 bit instruction set Optimized for code density from C code Improved performance form narrow memory Subset of the functionality of the ARM instruction set Core has two execution states ARM and Thumb Switch between them using BX instruction Thumb has characteristic features Most Thumb instruction are executed unconditionally Many Thumb data process instruction use a 2 address format Thumb instruction formats are less regular than ARM instruction formats as a result of the dense encoding 4 EE382N 4 Embedded Systems Architecture Processor Modes The ARM has six operating modes User unprivileged mode under which most tasks run FIQ entered when a high priority fast interrupt is raised IRQ entered when a low priority normal interrupt is raised Supervisor entered on reset and when a Software Interrupt instruction is executed Abort used to handle memory access violations Undef used to handle undefined instructions ARM Architecture Version 4 adds a seventh mode System privileged mode using the same registers as user mode 8 22 2008 5 EE382N 4 Embedded Systems Architecture The Registers ARM has 37 registers in total all of which are 32 bits long 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers However these are arranged into several banks with the accessible bank being governed by the processor mode Each mode can access a particular set of r0 r12 registers a particular r13 the stack pointer and r14 link register r15 the program counter cpsr the current program status register And privileged modes can also access a particular spsr saved program status register 8 22 2008 6 EE382N 4 Embedded Systems Architecture The ARM Register Set Current Visible Registers Abort Mode Undef SVC Mode IRQ FIQ Mode User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 sp r14 lr r15 pc cpsr spsr 8 22 2008 Banked out Registers User FIQ IRQ SVC Undef Abort r8 r9 r10 r11 r12 r13 sp r14 lr r8 r9 r10 r11 r12 r13 sp r14 lr r13 sp r14 lr r13 sp r14 lr r13 sp r14 lr r13 sp r14 lr spsr spsr spsr spsr spsr 7 EE382N 4 Embedded Systems Architecture Register Organization Summary User r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 sp r14 lr r15 pc FIQ User mode r0 r7 r15 and cpsr r8 r9 IRQ User mode r0 r12 r15 and cpsr SVC User mode r0 r12 r15 and cpsr Undef User mode r0 r12 r15 and cpsr Abort User mode r0 r12 r15 and cpsr Thumb state Low registers Thumb state High registers r10 r11 r12 r13 sp r13 sp r13 sp r13 sp r13 sp r14 lr r14 lr r14 lr r14 lr r14 lr spsr spsr spsr spsr spsr cpsr Note System mode uses the User mode register set 8 22 2008 8 EE382N 4 Embedded Systems Architecture Accessing Registers using ARM Instructions No breakdown of currently accessible registers All instructions can access r0 r14 directly Most instructions also allow use of the PC Specific instructions to allow access to CPSR and SPSR Note When in a privileged mode it is also possible to load store the banked out user mode registers to or from memory 8 22 2008 9 EE382N 4 Embedded Systems Architecture The Program Status Registers CPSR and SPSRs 31 28 4 8 N Z CV I F T 0 Mode Copies of the ALU status flags latched if the instruction has the S bit set 8 22 2008 Condition Code Flags N Negative result from ALU flag Z Zero result from ALU flag C ALU operation Carried out V ALU operation oVerflowed Mode Bits M 4 0 define the processor mode Interrupt Disable bits I 1 disables the IRQ F 1 disables the FIQ T Bit Architecture v4T only T 0 Processor in ARM state T 1 Processor in Thumb state 10 EE382N 4 Embedded Systems Architecture Condition Flags Logical Instruction Arithmetic Instruction Negative N 1 No meaning Bit 31 of the result has been set Indicates a negative number in signed operations Zero Z 1 Result is all zeroes Result of operation was zero Carry C 1 After Shift operation 1 was left in carry flag Result was greater than 32 bits oVerflow V 1 No meaning Result was greater than 31 bits Indicates a possible corruption of the sign bit in signed numbers Flag 8 22 2008 11 EE382N 4 Embedded Systems Architecture The Program Counter R15 When the processor is executing in ARM state All instructions are 32 bits in length All instructions must be word aligned Therefore the PC value is stored in bits 31 2 with bits 1 0 equal to zero as instruction cannot be halfword or byte aligned R14 is used as the subroutine link register LR and stores the return address when Branch with Link operations are performed calculated from the PC Thus to return from a linked branch MOV r15 r14 or MOV pc lr 8 22 2008 12 EE382N 4 Embedded Systems Architecture Exception Handling and the Vector Table When an exception occurs the core Copies CPSR into SPSR mode Sets appropriate CPSR bits If core implements ARM Architecture 4T and is currently in Thumb state then ARM state is entered Mode field bits Interrupt disable flags if appropriate Maps in appropriate banked registers Stores the return address in LR mode Sets PC to vector address To return exception handler needs to Restore CPSR from SPSR mode Restore PC from LR mode 8 22 2008 13 EE382N 4 Embedded Systems Architecture The Original Instruction Pipeline The ARM uses a pipeline in order to increase the speed of the flow of instructions to the processor Allows several operations to be undertaken simultaneously rather than serially PC FETCH PC 4 DECODE PC