S T E L L A R I S E R R ATA Stellaris LM3S2110 RevA2 Errata This document contains known errata at the time of publication for the Stellaris LM3S2110 microcontroller The table below summarizes the errata and lists the affected revisions See the data sheet for more details See also the ARM Cortex M3 errata ARM publication number PR326 PRDC 009450 v2 0 Date Revision September 2010 2 10 Minor edits and clarifications July 2010 2 9 Added issue The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled on page 10 June 2010 2 8 Added issue External reset does not reset the XTAL to PLL Translation PLLCFG register on page 4 May 2010 2 7 Minor edits and clarifications April 2010 2 6 Minor edits and clarifications April 2010 2 5 Removed issue Setting Bit 7 in I2C Master Timer Period I2CMTPR register may have unexpected results The data sheet description has changed such that this is no longer necessary Minor edits and clarifications Added issue The General Purpose Timer match register does not function correctly in 32 bit mode on page 10 Added issue Setting Bit 7 in I2C Master Timer Period I2CMTPR register may have unexpected results Hard Fault possible when waking from Sleep or Deep Sleep modes and Cortex M3 Debug Access Port DAP is enabled has been removed and the content added to the LM3S2110 data sheet February 2010 2 4 Description Jan 2010 2 3 Dec 2009 2 2 Started tracking revision history Erratum Number Erratum Title Revision s Affected 1 1 JTAG pins do not have internal pull ups enabled at power on reset A1 A2 1 2 JTAG INTEST instruction does not work A1 A2 2 1 Clock source incorrect when waking up from Deep Sleep mode in some configurations A1 A2 2 2 PLL may not function properly at default LDO setting A1 A2 2 3 I O buffer 5 V tolerance issue A1 A2 2 4 PLL Runs Fast When Using a 3 6864 MHz Crystal A1 A2 2 5 External reset does not reset the XTAL to PLL Translation PLLCFG register A1 A2 3 1 Hibernation module WAKE input pin does not work as specified September 05 2010 Rev 2 10 http www k ext ti com sc technical support product information centers htm A1 1 Texas Instruments Stellaris LM3S2110 A2 Errata Erratum Number Erratum Title Revision s Affected 3 2 Hibernation module low VBAT detection does not work as expected A1 A2 3 3 Performing a system wide reset also resets the Hibernation module and all of its registers A1 A2 3 4 Hibernation module may have higher current draw than specified in data sheet under certain conditions A1 A2 3 5 Hibernation module returns from the Hibernation state to the Wake state regardless of the status of the VDD supply to the microcontroller A1 A2 3 6 Certain Hibernation module register writes cause RTC Counter register inaccuracy A1 A2 3 7 Hibernation module state retention registers may corrupt after Wake sequence A1 A2 4 1 GPIO input pin latches in the Low state if pad type is open drain A1 A2 4 2 GPIO pins may glitch during power supply ramp up A1 A2 5 1 General purpose timer Edge Count mode count error when timer is disabled A1 A2 5 2 General purpose timer 16 bit Edge Count mode does not load reload value A1 A2 5 3 The General Purpose Timer match register does not function correctly in 32 bit mode A1 A2 6 1 The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled 7 1 CAN register accesses require software delays A1 A2 8 1 PWM pulses cannot be smaller than dead band time A1 A2 8 2 PWM interrupt clear misses in some instances A1 A2 8 3 PWM generation is incorrect with extreme duty cycles A1 A2 8 4 PWMINTEN register bit does not function correctly A1 A2 8 5 Sync of PWM does not trigger zero action A1 A2 8 6 PWM zero action occurs when the PWM module is disabled A1 A2 A2 1 JTAG and Serial Wire Debug 1 1 JTAG pins do not have internal pull ups enabled at power on reset Description Following a power on reset the JTAG pins TRST TCK TMS TDI and TDO PB7 and PC 3 0 do not have internal pull ups enabled Consequently if these pins are not driven from the board two things may happen The JTAG port may be held in reset and communication with a four pin JTAG based debugger may be intermittent or impossible The receivers may draw excess current Workaround There are a number of workarounds for this problem varying in complexity and impact 1 Add external pull up resistors to all of the affected pins This workaround solves both issues of JTAG connectivity and current consumption 2 Texas Instruments September 05 2010 Rev 2 10 http www k ext ti com sc technical support product information centers htm Stellaris LM3S2110 A2 Errata 2 Add an external pull up resistor to TRST Firmware should enable the internal pull ups on the affected pins by setting the appropriate PUE bits of the appropriate GPIO Pull Up Select GPIOPUR registers as early in the reset handler as possible This workaround addresses the issue of JTAG connectivity but does not address the current consumption other than to limit the affected period from power on reset to code execution 3 Pull ups on the JTAG pins are unnecessary for code loaded via the SWD interface or via the serial boot loader Loaded firmware should enable the internal pull ups on the affected pins by setting the appropriate PUE bits of the appropriate GPIOPUR registers as early in the reset handler as possible This method does not address the current consumption other than to limit the affected period from power on reset to code execution Silicon Revision Affected A1 A2 1 2 JTAG INTEST instruction does not work Description The JTAG INTEST Boundary Scan instruction does not properly capture data Workaround None Silicon Revision Affected A1 A2 2 System Control 2 1 Clock source incorrect when waking up from Deep Sleep mode in some configurations Description In some clocking configurations the core prematurely starts executing code before the main oscillator MOSC has stabilized after waking up from Deep Sleep mode This situation can cause undesirable behavior for operations that are frequency dependent such as UART communication This issue occurs if the system is configured to run off the main oscillator with the PLL bypassed and the DSOSCSRC field of the Deep Sleep Clock Configuration DSLPCLKCFG register set to use the internal 12 MHz oscillator 30 KHz internal oscillator or 32 KHz external oscillator When the system is triggered to wake up the core should wait for the main oscillator to stabilize before starting to execute code Instead the core starts executing code while being clocked from the deep