1 JTAG and Serial Wire Debug2 System Control3 Hibernation Module4 GPIO5 General-Purpose Timers6 UART7 CAN8 PWMSTELLARIS ERRATAStellaris®LM3S2110 RevA2 ErrataThis document contains known errata at the time of publication for the Stellaris®LM3S2110microcontroller. The table below summarizes the errata and lists the affected revisions. See thedata sheet for more details.See also the ARM® Cortex™-M3 errata, ARM publication number PR326-PRDC-009450 v2.0.DescriptionRevisionDate■ Minor edits and clarifications.2.10September 2010■ Added issue “The RTRIS bit in the UARTRIS register is only set when the interrupt isenabled” on page 10.2.9July 2010■ Added issue “External reset does not reset the XTAL to PLL Translation (PLLCFG)register” on page 4.2.8June 2010■ Minor edits and clarifications.2.7May 2010■ Minor edits and clarifications.2.6April 2010■ Removed issue "Setting Bit 7 in I2C Master Timer Period (I2CMTPR) register may have unexpectedresults". The data sheet description has changed such that this is no longer necessary.■ Minor edits and clarifications.2.5April 2010■ Added issue “The General-Purpose Timer match register does not function correctly in 32-bitmode” on page 10.■ Added issue "Setting Bit 7 in I2C Master Timer Period (I2CMTPR) register may have unexpectedresults".2.4February 2010■ "Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3 Debug AccessPort (DAP) is enabled" has been removed and the content added to the LM3S2110 data sheet.2.3Jan 2010Started tracking revision history.2.2Dec 2009Revision(s) AffectedErratum TitleErratumNumberA1, A2JTAG pins do not have internal pull-ups enabled at power-on reset1.1A1, A2JTAG INTEST instruction does not work1.2A1, A2Clock source incorrect when waking up from Deep-Sleep mode in some configurations2.1A1, A2PLL may not function properly at default LDO setting2.2A1, A2I/O buffer 5-V tolerance issue2.3A1, A2PLL Runs Fast When Using a 3.6864-MHz Crystal2.4A1, A2External reset does not reset the XTAL to PLL Translation (PLLCFG) register2.5A1Hibernation module WAKE input pin does not work as specified3.11Texas InstrumentsSeptember 05, 2010/Rev. 2.10http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htmRevision(s) AffectedErratum TitleErratumNumberA1, A2Hibernation module low VBAT detection does not work as expected3.2A1, A2Performing a system-wide reset also resets the Hibernation module and all of its registers3.3A1, A2Hibernation module may have higher current draw than specified in data sheet undercertain conditions3.4A1, A2Hibernation module returns from the Hibernation state to the Wake state regardless ofthe status of the VDD supply to the microcontroller3.5A1, A2Certain Hibernation module register writes cause RTC Counter register inaccuracy3.6A1, A2Hibernation module state retention registers may corrupt after Wake sequence3.7A1, A2GPIO input pin latches in the Low state if pad type is open drain4.1A1, A2GPIO pins may glitch during power supply ramp up4.2A1, A2General-purpose timer Edge Count mode count error when timer is disabled5.1A1, A2General-purpose timer 16-bit Edge Count mode does not load reload value5.2A1, A2The General-Purpose Timer match register does not function correctly in 32-bit mode5.3A2The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled6.1A1, A2CAN register accesses require software delays7.1A1, A2PWM pulses cannot be smaller than dead-band time8.1A1, A2PWM interrupt clear misses in some instances8.2A1, A2PWM generation is incorrect with extreme duty cycles8.3A1, A2PWMINTEN register bit does not function correctly8.4A1, A2Sync of PWM does not trigger "zero" action8.5A1, A2PWM "zero" action occurs when the PWM module is disabled8.61 JTAG and Serial Wire Debug1.1 JTAG pins do not have internal pull-ups enabled at power-on resetDescription:Following a power-on reset, the JTAG pins TRST, TCK, TMS, TDI, and TDO (PB7 and PC[3:0]) donot have internal pull-ups enabled. Consequently, if these pins are not driven from the board, twothings may happen:■ The JTAG port may be held in reset and communication with a four-pin JTAG-based debuggermay be intermittent or impossible.■ The receivers may draw excess current.Workaround:There are a number of workarounds for this problem, varying in complexity and impact:1. Add external pull-up resistors to all of the affected pins. This workaround solves both issues ofJTAG connectivity and current consumption.September 05, 2010/Rev. 2.10http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm2Texas InstrumentsStellaris®LM3S2110 A2 Errata2. Add an external pull-up resistor to TRST. Firmware should enable the internal pull-ups on theaffected pins by setting the appropriate PUE bits of the appropriate GPIO Pull-Up Select(GPIOPUR) registers as early in the reset handler as possible. This workaround addresses theissue of JTAG connectivity, but does not address the current consumption other than to limitthe affected period (from power-on reset to code execution).3. Pull-ups on the JTAG pins are unnecessary for code loaded via the SWD interface or via theserial boot loader. Loaded firmware should enable the internal pull-ups on the affected pins bysetting the appropriate PUE bits of the appropriate GPIOPUR registers as early in the resethandler as possible. This method does not address the current consumption other than to limitthe affected period (from power-on reset to code execution).Silicon Revision Affected:A1, A21.2 JTAG INTEST instruction does not workDescription:The JTAG INTEST (Boundary Scan) instruction does not properly capture data.Workaround:None.Silicon Revision Affected:A1, A22 System Control2.1 Clock source incorrect when waking up from Deep-Sleep mode insome configurationsDescription:In some clocking configurations, the core prematurely starts executing code before the main oscillator(MOSC) has stabilized after waking up from Deep-Sleep mode. This situation can cause undesirablebehavior for operations that are frequency dependent, such as UART communication.This issue occurs if the system is configured to run off the main oscillator, with the PLL bypassedand the DSOSCSRC field of the Deep-Sleep Clock Configuration (DSLPCLKCFG) register set touse the internal 12-MHz oscillator, 30-KHz internal oscillator, or 32-KHz external oscillator. Whenthe system is triggered to wake up, the core should wait for the main oscillator to stabilize beforestarting