AbstractIntroductionDMAC with Forward Source, Fixed DestinationConfiguring the DMAC for Forward Source, Fixed DestinationReferenceSoftware CodeAPPLICATION NOTE M16C/62 Using the M16C/62 DMAC in Forward Source Mode 1.0 Abstract The following article introduces and shows an example of how to use the DMAC function of the M16C/62 with a forward counting source address and fixed destination address. 2.0 Introduction The Renesas M16C/62 is a 16-bit MCU based on the M16C CPU core with 256 KB of user Flash. The MCU has two DMAC (Direct Memory Access Controller) channels that allow data to be transferred from a source memory location to a destination memory location without using the CPU. The DMAC utilizes the same internal address and data busses as the CPU yet is given a higher priority to the data bus than the CPU. This method of DMAC and CPU bus arbitration is termed a cycle stealing method. Each DMAC controller is capable of transferring data to or from a fixed address to any other address in the 1Mbyte address space. The DMAC controllers can automatically transfer 128k bytes of data using word (16-bit) transfers, or 64k bytes of data using byte (8-bit) transfers. The source or destination address can also be auto-incremented. DMAC transfers can be initiated by an interrupt request signal or by manually writing to the software DMA request bit. When requests are initiated by an interrupt request signal, neither the interrupt enable flag (I flag) nor the interrupt priority level affects the DMA transfers. 3.0 DMAC with Forward Source, Fixed Destination In the forward source counting address, fixed destination address mode, the DMAC controller will transfer bytes or words from an incrementing source address (that increments after each transfer) to a fixed destination address. The transfers can be either bytes or words. Loading a value into the transfer count register controls the number of automated transfers. Transfers will continue to occur each time the DMAC trigger event occurs until the transfer register underflows, therefore the number loaded into the register should be 1 less than the number of transfers desired. A control register bit determines whether each transfer is a byte or word of data. When the DMAC controller is configured to perform a single transfer cycle, the DMAC becomes disabled after the transfer register underflows. In the repeat mode the Source Pointer register and the Transfer Counter register are reloaded with their initial values after the Transfer Counter register underflows and the DMAC remains active. Therefore, in the repeat mode, transfers will occur each time a trigger event occurs until the DMA enable bit is set inactive ("0"). REU05B0010-0100Z June 2003 Page 1 of 6M16C/62Using the M16C/62 DMAC in Forward Source Mode 4.0 Configuring the DMAC for Forward Source, Fixed Destination To configure a DMAC channel, the following choices must be configured (the configurations for this example are shown in parentheses): 1. Select the DMA request cause (UART0 receive interrupt request). 2. Select fixed or forward source (forward source). 3. Select fixed or forward destination (fixed destination). 4. Select 8 or 16-bit transfers (8-bit transfers). 5. Select a single transfer or multiple transfers (single transfer). 6. Select the source address for the transfer (Buffer address in RAM). 7. Select the destination address for the transfer UART0 transmit buffer address). 8. Select the number of bytes to be transferred (10). The registers that are used to configure and control the DMAC channels are shown in . Figure 1Figure 1 DMA0 Request Cause Select Register DMA0 request cause select registerSymbol Address When resetDM0SL 03B8160016FunctionBit symbolb7 b6 b5 b4 b3 b2 b1 b0DMA request cause select bitDSEL0RWDSEL1DSEL2DSEL3Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.Software DMA request bitIf software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”)DSRb3 b2 b1 b00 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger0 0 1 0 : Timer A00 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0)/two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0)Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0)Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit Bit nameDMA request cause expansion select bitDMS0 : Normal1 : Expanded cause REU05B0010-0100Z June 2003 Page 2 of 6M16C/62Using the M16C/62 DMAC in Forward Source Mode DMA1 request cause select registerSymbol Address When resetDM1SL 03BA160016FunctionBit symbolb7 b6 b5 b4 b3 b2 b1 b0DMA request cause select bitDSEL0RWDSEL1DSEL2DSEL3Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.Software DMA request bitIf software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”)DSRb3 b2 b1 b00 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger0 0 1 0 : Timer A00 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0)/serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0)/serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive Bit nameDMA request cause expansion select bitDMS0 : Normal1 : Expanded cause DMAi control registerSymbol Address When resetDMiCON(i=0,1) 002C16, 003C1600000X002Bit name F unctionBit symbolTransfer unit bit select bitb7 b6 b5 b4 b3 b2 b1 b00 : 16 bits1 : 8 bitsDMBIT RWDMASLDMASDMAERepeat transfer mode select bit0 : Single transfer1 : Repeat transferDMA request bit (Note 1)0 : DMA not requested1 : DMA requested0 : Disabled1 : Enabled0 : Fixed1 : ForwardDMA enable bitSource address direction select bit (Note 3)Destination address direction select bit (Note 3)0 : Fixed1 : ForwardDSDDADNothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.Note 1: DMA request can be cleared by resetting the bit.Note 2: This bit can only be set to “0”.Note 3: Source
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