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AbstractIntroductionPower Conservation: IntroductionM16C: IntroductionPower Control ModesImplementation: HardwareImplementation: SoftwareReferenceSoftware CodeAPPLICATION NOTE M16C/62 Using the M16C/62 Power Saving Modes 1.0 Abstract This article discusses the various power saving modes of the M16C device. A short program is provided that can be run on the MSV3062 development board. Using an Amp meter connected to a special header, it is possible to measure only the current that the device uses. Thus the power consumption can be read, with the device in various clock modes and operating modes. 2.0 Introduction Several power saving modes are critical, especially for battery-operated products. Products need to operate at full speed when required, as well as be able to go into the lowest power consuming sleep state. Intermediate states are also necessary for tasks not requiring full speed, thus conserving power. 3.0 Power Conservation: Introduction Power conservation is accomplished three ways. The main clock can operate from the high speed or low speed crystal at various divided speeds (gears). WAIT mode is the next feature that allows power to be conserved, while still letting the peripherals function. STOP mode is the lowest power conserving mode, drawing the least amount of current, yet allowing the device to wake up and go back to full speed. 4.0 M16C: Introduction The M16C family is designed from the beginning for low power consumption. These devices are single-chip microcomputers, built using the high-performance silicon gate CMOS process technology. They use sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space (/62 series), up to 16M bytes of address space (/80 series), and operation voltages from 2.7V to 5V, they are capable of executing from 16 MHz to 20 MHz. Other features include single-voltage Flash, a built-in multiplier, DMAC, 10 channels of A/D, and over 5 channels of serial I/O, making them ideal for industrial equipment, communications, and other high-speed processing applications requiring careful power management. 4.1 M16C: WAIT Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters WAIT mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop, so the peripherals using fC32 do not contribute to the power saving. When the MCU is running in low-speed or low REU05B0017-0100Z June 2003 Page 1 of 11M16C/62Using the M16C/62 Power Saving Modes power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1 shows the status of the ports in WAIT mode. Table 1 Port status during WAIT mode Pin Memory expansion mode Microprocessor mode Single-chip mode Address bus, data bus, CS0, CS3, BHE Retains status before WAIT mode RD, WR, WRL, WRH “H” HLDA, BCLK “H” ALE “H” Port Retains status before WAIT mode Retains status before WAIT mode CLKOUT When fc selected Valid only in single-chip mode Does not stop When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering WAIT mode is maintained. WAIT mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel WAIT mode, that interrupt must first have been enabled, and the priority level of the interrupts that are not used to cancel must have been changed to 0. If returning by an interrupt, the clock during which the WAIT instruction executed is set to BCLK by the microcomputer and the action is resumed from the interrupt routine. If only a hardware RESET or an NMI interrupt is used to cancel WAIT mode, change the priority level of all interrupts to 0, and then shift to WAIT mode. 4.2 M16C: STOP Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters STOP mode. In STOP mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD, stops in STOP mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4 also function provided an external clock is selected. Table 2 shows the status of the ports in STOP mode. REU05B0017-0100Z June 2003 Page 2 of 11M16C/62Using the M16C/62 Power Saving Modes Table 2 Port status during STOP mode Pin Memory expansion mode Microprocessor mode Single-chip mode Address bus, data bus, CS0, CS3, BHE Retains status before STOP mode RD, WR, WRL, WRH “H” HLDA, BCLK “H” ALE “H” Port Retains status before STOP mode Retains status before STOP mode CLKOUT When fc selected Valid only in single-chip mode “H” When f8, f32 selected Valid only in single-chip mode Retains status before STOP mode STOP mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel STOP mode, that interrupt must first have been enabled, and the priority level of the interrupt that is not used to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a hardware RESET or an NMI interrupt is used to cancel STOP mode, change the priority level of all interrupts to 0, and then shift to STOP mode. When shifting from high-speed/medium-speed mode to STOP mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode to STOP mode, the value before STOP mode is retained. 4.3 M16C: Main Clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive


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