Memory ExpansionEmbedded SystemsLecture 2222-1In These Notes . . . Memory TypesMemory Expansion– Interfacing• Parallel• SerialDirect Memory Access controllersEmbedded Systems 22-2Memory Characteristics and IssuesVolatility - Does it remember when the power fails?Persistence - How long does it remember when there is power?Speed – How quickly can it be read or written?Reprogrammability– Speed is often an issue for nonvolatile memories–Maximum number of W/E cyclesEmbedded Systems–Maximum number of W/E cycles– Programming voltageCostTemperature Sensitivity - EPROMs forget at high temperatures22-3Types of Memory - ROMMask– A custom ROM mask pattern is created– Large minimum order, NRE costsPROM– Program by burning fuses. Apply a high voltage for a certain amount of time.– Not erasableEmbedded SystemsUV EPROM– Program by squeezing charge into floating transistor gate with high voltage – Erase entire memory at once with UV radiation22-4Types of Memory - EEPROMEEPROM– Can erase a byte at a time electrically– Limited reprogrammability: e.g. 100,000 cycles– Slow programming (up to 10 ms per byte)Flash EEPROM– Can erase entire chip, or just certain blocks–May have limited reprogrammability: e.g. 1,000 cycles for some Embedded Systems–May have limited reprogrammability: e.g. 1,000 cycles for some low-end units– May have slow programming– Serial or parallel interface22-5Types of Memory - RAMSRAM– Use two or six transistors per bit– Fast - 10 ns or lessDRAM– Use one transistor per bit– Acts like a capacitor, discharges in a few milliseconds–Incredibly cheap, but need to refresh each bit periodicallyEmbedded Systems–Incredibly cheap, but need to refresh each bit periodically– Slower than SRAM - 60 ns– Tricks to speed up access (e.g. page mode)22-6Parallel Memory Interface1920 bytes are not enough for our data logger!We want to store up to 32 kBytes of dataChoose a microcontroller with more memory?– Not available, or too expensiveInstead choose a microcontroller Embedded Systemswith a memory expansion mode– M16C/62Modes for M16C/62 MCU22-7SRAM Example – IDT71256L32k x 8 SRAMEmbedded Systems 22-8IDT71256L Read TimingEmbedded SystemsSymbol Parameter Minimum (ns) Maximum (ns)tRCRead Cycle Time 20 -tAAAddress Access time - 20tOLZOutput Enable to Output in Low-Z 2 -tOEOutput Enable to Output Valid - 10tOHZOutput Disable to Output in Hi-Z 2 822-9IDT71256L Write TimingEmbedded SystemsSymbol Parameter Minimum (ns) Maximum (ns)twcWrite Cycle Time 20 -tAWAddress Valid to End-of-Write 15 -tWPWrite Pulse Width 15 -tASAddress Set-Up Time 0 -tDWData to Write Time Overlap 11 -tDHData Hold from Write Time 0 -22-10External Memory Access – Separate BusesChip Select– Partial vs. Full Decoding– Power ConsumptionMCU SRAMI/O7-I/O0D7-D0A14-A0 A14-A0~WR ~WE~RD ~OE~CSA15Embedded SystemsD7-D0A15-A0~WR~RDReadWriteData from SRAMAdx from MCU Adx from MCUData from MCU22-11External Memory Access – Multiplexed BusesUse a latch to hold the low byte of the addressSaves pinsMCUSRAMI/O7-I/O0AD7-AD0A14-A8A14-A8~WR ~WE~RD ~OE~CSReadWriteA15A7-A0ALEEmbedded SystemsAD7-AD0A15-A8~WR~RDReadWriteHi Adx from MCU Hi Adx from MCULatch OutLow Adx from MCUALELow Adx SRAM D Low Adx MCU DLow Adx from MCU22-12Multiple External MemoriesMCU SRAM 1I/O7-I/O0D7-D0A14-A0 A14-A0~WR ~WE~RD~OE~CSA16-A15SRAM 2I/O7-I/O0A14-A0~WE~OE~CSROM 1I/O7-I/O0A14-A0~OE~CSEmbedded SystemsDecoder selects a single memory chip– Output 0 active when A16:A15 = 00. Address = 0 0xxx xxxx xxxx xxxx = 00000h to 07FFFh– Output 1 active when A16:A15 = 01. Address = 0 1xxx xxxx xxxx xxxx = 08000h to 0FFFFh– Output 2 active when A16:A15 = 10. Address = 1 0xxx xxxx xxxx xxxx = 10000h to 17FFFh~RD~OE~OE~OEDecoder01 222-13Issue – Bus LoadingMicrocontroller has a limited output drive capacity on the data and address buses– e.g. 100 pF for an AMD MCUEach device on the bus adds capacitance – 11 pF for each input on IDT SRAM chipThis leads to increased time delay until bus reaches valid voltageEmbedded Systemsvoltage– M16C lowers threshold voltages when accessing external memorySolution: add buffers22-14Issue - The Memory WallDifference in read cycle times for memories– Internal memories• SRAM: blazingly fast• Flash: down to 40 ns– External parallel-interface memories• SRAM: down to 10 ns•Flash: down to 55 nsEmbedded Systems•Flash: down to 55 nsMemory Wall: flash memory can’t keep up with fast processors– External flash: 1/55 ns = 18 MHz– Internal flash: 1/40 ns = 25 MHzNeed a mechanism to speed up access to data stored in flash memory22-15Solutions to the Embedded Memory WallCode shadowing– Use flash memory to hold the program– At boot-time load the program into faster SRAM– Execute the program out of SRAM– Problem: extra memory costs moneyCache– Use a small fast SRAM with a cache controller to hold commonly used data– Problem: unpredictable access times make it hard to guarantee predictable timing (e.g. real-time is difficult)Embedded Systemsreal-time is difficult)Wider bus to memory– Access multiple (e.g. four bytes) at a time. – Fetching byte N also prefetches bytes N+1, N+2 and N+3– Works well for sequential accesses– Problem: Still incurs a delay for random accesses (e.g. branch)Branch target cache– Cache multiple bytes from targets of branch instructions– Problem: Unpredictable access times. But may be able to lock cache.– Could also cache the beginning of all ISRs22-16Storing Large Amounts of DataWhat if we want to store more data than fits into our processor’s address space?A. Use a memory paging scheme • Use a register (or output port) to hold the upper bits of the address– This register selects which page of memory we will access• Control the register with a page select function• This doesn’t fit in well with C, as the compiler doesn’t know about your custom paging scheme–Some MCUs support paging, and the compilers can compile for itEmbedded Systems–Some MCUs support paging, and the compilers can compile for itB. Use a serially-interfaced memory (inexpensive)• Communicate with the memory over a few data lines• C compiler doesn’t know about this memory either– May want to introduce some kind of file system to manage information in the expanded memory22-17Serial Interface FlashNOR Flash Memory Array with Small PagesRESETRESET input input allows the allows the System to System to Terminate Any Terminate Any
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