1Flip-Flops and Sequential Circuit DesignECE 152A – Summer 2009July 27, 2009ECE 152A - Digital Design Principles2Reading AssignmentBrown and Vranesic7 Flip-Flops, Registers, Counters and a Simple Processor7.5 T Flip-Flop7.5.1 Configurable Flip-Flops7.6 JK Flip-Flop7.7 Summary of Terminology7.8 Registers7.8.1 Shift Register7.8.2 Parallel-Access Shift Register2July 27, 2009ECE 152A - Digital Design Principles3Reading AssignmentBrown and Vranesic (cont)7 Flip-Flops, Registers, Counters and a Simple Processor (cont)7.9 Counters7.9.1 Asynchronous Counters7.9.2 Synchronous Counters7.9.3 Counters with Parallel Load7.10 Reset SynchronizationJuly 27, 2009ECE 152A - Digital Design Principles4Reading AssignmentBrown and Vranesic (cont)7 Flip-Flops, Registers, Counters and a Simple Processor (cont)7.11 Other Types of Counters7.11.1 BCD Counter7.11.2 Ring Counter7.11.3 Johnson Counter7.11.4 Remarks on Counter Design3July 27, 2009ECE 152A - Digital Design Principles5Reading AssignmentBrown and Vranesic (cont)8 Synchronous Sequential Circuits8.1 Basic Design Steps8.1.1 State Diagram8.1.2 State Table8.1.3 State Assignment8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions8.1.5 Timing Diagram8.1.6 Summary of Design StepsJuly 27, 2009ECE 152A - Digital Design Principles6Reading AssignmentBrown and Vranesic (cont)8 Synchronous Sequential Circuits (cont)8.2 State-Assignment ProblemOne-Hot Encoding8.7 Design of a Counter Using the Sequential Circuit Approach8.7.1 State Diagram and State Table for Modulo-8 Counter8.7.2 State Assignment8.7.3 Implementation Using D-Type Flip-Flops8.7.4 Implementation Using JK-Type Flip-Flops8.7.5 Example – A Different Counter4July 27, 2009ECE 152A - Digital Design Principles7Reading AssignmentRoth11 Latches and Flip-Flops11.5 S-R Flip-Flop11.6 J-K Flip-Flop11.7 T Flip-Flop11.8 Flip-Flops with Additional Inputs11.9 Summary12 Registers and Counters12.5 Counter Design Using S-R and J-K Flip-Flops12.6 Derivation of Flip-Flop Input Equations – SummaryJuly 27, 2009ECE 152A - Digital Design Principles8The JK Flip-FlopAllows J = K = 1 conditionImplemented with a gated SR latch and feedback of Q and Q*Q toggles (Q+= Q’) on J = K = 15July 27, 2009ECE 152A - Digital Design Principles9The JK Flip-Flop (cont)Characteristic table and equationKarnaugh map of characteristic tableCharacteristic equationQ+= JQ’ + K’QJuly 27, 2009ECE 152A - Digital Design Principles10The JK Flip-Flop (cont)Implementation using a D flip-flopCharacteristic Function at D input6July 27, 2009ECE 152A - Digital Design Principles11The JK Flip-FlopState table1110(Q+)001110001101JK = 00PS (Q)NSJuly 27, 2009ECE 152A - Digital Design Principles12The JK Flip-FlopState diagram10JK = X1JK = 1XJK = 0XJK = X07July 27, 2009ECE 152A - Digital Design Principles13The JK Flip-FlopWith clock circuitry and timingPositive edge triggered JK flip-flopJuly 27, 2009ECE 152A - Digital Design Principles14The Master Slave JK Flip-FlopMaster Slave JK Flip-FlopRising edge triggerednote CLK inverted to master8July 27, 2009ECE 152A - Digital Design Principles15The Master Slave JK Flip-FlopMaster Slave JK Flip-FlopFalling edge triggerednote CLK (CP) inverted to slaveJuly 27, 2009ECE 152A - Digital Design Principles16The Master Slave JK Flip-FlopMaster active on CLK = 1Slave active on CLK = 0Latch data in master on CLK = 1Transfer data to slave (output) on CLK = 0Timing Diagram Initial ConditionsCLK = 0, J = 1, K = 0, Y = 0, Q = 09July 27, 2009ECE 152A - Digital Design Principles17The Master Slave JK Flip-FlopTiming DiagramJuly 27, 2009ECE 152A - Digital Design Principles18The JK Flip-Flop (cont)What happens if J = K = 1 for an indefinite period of time (i.e., much greater than clock period)?Output oscillates at ½ the frequency of the clockDivide by two counter10July 27, 2009ECE 152A - Digital Design Principles19The T (Toggle or Trigger) Flip-FlopConnect J and K inputs togetherCombined input “T”Characteristic TableCharacteristicEquationTimingDiagramJuly 27, 2009ECE 152A - Digital Design Principles20The T Flip-FlopState Table011100T=1T = 0PS (Q)NS (Q+)11July 27, 2009ECE 152A - Digital Design Principles21The T Flip-FlopState Diagram10T = 1T = 1T = 0T = 0July 27, 2009ECE 152A - Digital Design Principles22The T Flip-Flop (from JK/D)Q+= JQ’ + K’QQ+= T’Q + TQ’ = T XOR Q12July 27, 2009ECE 152A - Digital Design Principles23Counter Design with T Flip-Flops3 bit binary counter design example“State” refers to Q’s of flip-flops3 bits, 8 statesDecimal 0 through 7No inputsTransition on every clock edgei.e., state changes on every clock edgeAssume clocked, synchronous flip-flopsJuly 27, 2009ECE 152A - Digital Design Principles24Counter Design with T Flip-FlopsState Diagram001100011010111000110 10113July 27, 2009ECE 152A - Digital Design Principles25Counter Design with T Flip-FlopsState table000111111011011101101001001110110010010100100000C+B+A+CBANSPSJuly 27, 2009ECE 152A - Digital Design Principles26Counter Design with T Flip-FlopsNext State MapsBCA00 010111 101111BCA00 010111 10BCA00 010111 1011111111A+= AB’ + AC’ + A’BC = DAB+= B’C + BC’ = DBC+= C’ = DC14July 27, 2009ECE 152A - Digital Design Principles27Counter Design with T Flip-FlopsUsing D flip-flops, inputs are derived directly from next state mapsD = Q+Using T flip flopsExcitation table (used for design)T = Q XOR Q+Need to find inputs to T flip-flopsMapping state changesQ → Q+ requires T = ?July 27, 2009ECE 152A - Digital Design Principles28Counter Design with T Flip-FlopsT Flip-Flop Excitation TableT = Q XOR Q+011101110000TQ+Q15July 27, 2009ECE 152A - Digital Design Principles29Counter Design with T Flip-FlopsState Variable ATA= A+(XOR) ABCA00 01A=0A=111 10A+=1BCA00 010111 10T=1T=1A+=1A+=1A+=1A+= AB’ + AC’ + A’BC = DATA= BCJuly 27, 2009ECE 152A - Digital Design Principles30Counter Design with T Flip-FlopsState Variable BTB= B+(XOR) BBCA00 010111 10B+=1BCA00 010111 10T=1T=1B+=1B+=1B+=1B+= B’C + BC’ = DBTB= CB=0B=1T=1T=116July 27, 2009ECE 152A - Digital Design Principles31Counter Design with T Flip-FlopsState Variable CTC= C+(XOR) CBCA00 010111 10C+=1BCA00 010111 10T=1T=1C+=1C+=1C+=1C+=