ECE 152A LABORATORY 2 ________ Objectives :1. Understand the trade-off between time- and space-efficiency in the design of adders. In this lab, adders operate on unsigned numbers.2. Learn how to write Verilog code for different adder implementations. Apply the principles of hierarchical design. Verify each design by simulation.3. On an FPGA, implement a 4-bit adder that is made up of two 2-bit adders. The adder operates on unsigned numbers and should be able to detect overflow.Deliverables and Due Dates:Lab # 2 Problem Set is due at the beginning of your lab section when Lab # 2 starts. This comprises completing Part A below. (See the "Design Steps in Detail".)In addition, you have to come to the lab having read the rest of this lab (i.e. Part B). If you come to the lab having written the Verilog code for the three different implementations, you will get a head start on this lab. (Please note that we take the Honor Code very seriously: Copying Verilog code from someone outside your lab team will get you an F in this course and referral to the Committee on Student Misconduct. You must write the Verilog code with only your own team.)Lab # 2 check-out occurs in the following week. This comprises completing all of the remaining steps in this lab and demonstrating the correct functionality of your simulations and the final implementation in FPGA.Grading will be done as follows for steps completed on time:Part A: (due the beginning of the lab session when Lab # 2 starts.)Step A.1: 15%Step A.2: 15%Step A.3: 15%Step A.4: 5%Part B: (due the lab session in the following week.)Step B.1-B.2 for A.1: 10%Step B.1-B.2 for A.3: 15%Step B.3-B.4 for A.3: 25%The grades for Part B are based on demonstration of functionality for each step. For each step in Part B, partial credit will usually NOT be given.Design Strategy (Outline):Part A . We will compute the area and delay of three different implementations of the 4-bit adder by using the simple gate delay model.Step A.1 . Analysis of the ripple carry adder implementationStep A.2 . Analysis of the two-level AND-OR implementationStep A.3 . Analysis of two 2-bit adders in cascadeStep A.4 . ComparisonPart B . We will write the Verilog code for the implementations A.1 and A.3.For implementations A.1 and A.3, do the following steps:Step B.1: Write the design in Verilog.Step B.2: Simulate the design using Xilinx and verify operation.For implementation A.3, do the following steps in addition:Step B.3: Compile and download to the FPGA.Step B.4: Test the FPGA implementation and verify operation.Design Steps in Detail:Part A: Worst-case delay and area cost analysis of different implementationsIn this step, we will use analytical techniques and the simple gate delay model to compare three different implementations of the 4-bit adder with respect to their worst-case delay and area performance. (We will see more sophisticated adders such as the carry look-ahead adder later in the course. But the design of those adders use the same ideas of time- and space-efficiency.)In all of the steps below,(1) Your adder design must be able to detect overflow,(2) You should have a 1-bit carry-in to the 4-bit adder. (This way, you can cascade such 4-bit adders, if you want to build larger adders.)Step A.1 . In this step, we implement the 4-bit adder as four full-adders in cascade. This is called a "ripple carry adder" because the carry bit has to ripple from one element to the next. We expect that the worst-case delay of the ripple carry adder will be dominated by the carry chain. In this exercise, we want to quantify such intuitions.(a) Using the simple gate delay model (which associates a delay with each gate), find an expression for the maximum (i.e. worst-case) delay of the 4-bit ripple carry adder. In addition, find a "critical input transition" that will result in this maximum delay.(b) What is the number of 2-input gates that this implementation uses?(c) Your textbook uses an "area cost function" defined as the sum of the number of inputs that are input to all the gates in the circuit plus the number of gates in the circuit. This cost function is reasonable for CMOS VLSI implementation of adders because the wires on a CMOS chip add significantly to the area of the circuit. In fact, roughly 80% of the area of a VLSI chip today is consumed by wires and only 20% by transistors.Using this cost function, compute the area cost of this 4-bit adder implementation.Step A.2 . Now, we want to estimate the delay and the space-complexity of the 4-bit adder when it is designed as a combinational logic block from the truth table directly and then minimized using Karnaugh maps to arrive at a minimum sum-of-products expression for each output.The problem is that the truth table for this 4-bit adder is large. (How many rows does it have?) So, in this section, instead of finding the explicit expressions, we will try to estimate the delay and space-complexity.Without writing down the truth table, write the Boolean equation for each sum bit in terms of the internal carry bits. Now, we would have to substitute for these carry bits successively in terms of the inputs. You should do this substitution for sum[0] and sum[1]and see what results in terms of AND, OR, NOT gates. By doing this for sum[0] and sum[1], you should be able to see how fast these terms multiply. Now, try to visualize what the resulting circuit will look like, without finding the expressions for sum[2] and sum[3]. Sketch the schematic. Then, answer the following questions:(a) How many logic levels will there be in the final circuit?(b) What will be the dependency between the variables? For example, sum[0] depends on which input variables? And sum[1] depends on which input variables? Similarly, what input variables does each of sum[2] and sum[3] depend on? (c) In the final circuit, where do you expect the gates with large fan-in to be located? Where do you expect small fan-in?(d) Along which path do you expect the worst-case (maximum) delay to lie? Is this a result of the number of logic levels that the input signal has to travel through?(e) Estimate the number of gates and the area cost of this implementation.[You should be aware that there are tools that can automate 2-level logic minimization. The tool "espresso" available for free from Berkeley at http://www-cad.eecs.berkeley.edu/Software/software.html is such a tool. If you would like to experiment with it, you can download