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UCSB ECE 152A - State Machines

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15 STATE MACHINESSTATE MACHINE TYPESThere are two types of state machines: Mealy machines and Moore machines. Youcan model both types of machines in Verilog. The difference between Mealy andMoore machines is in how outputs are generated. In a Moore machine, the outputsare a function of the current state. This implies that the outputs from the Mooremachine are synchronous to the state changes. In a Mealy machine, the outputs area function of both the state and the inputs.A state machine can be broken down into three parts: The state register, the next-state logic, and the output logic.A state machine can be depicted as shown in Figure 15-1.170Verilog QuickstartFigure 15-1 can be modified to bring the inputs through to the output logic, thuscreating a Mealy state machine, as shown in Figure 15-2.To model a state machine in Verilog, you must model each of the three parts of thestate machine.State Machines171STATE MACHINE MODELING STYLEBecause a state machine is made up of three parts, you have a choice whether tomodel each section independently, or to try to combine the parts into one section ofthe model.Table 15-1 shows some interesting combinations:In the first style, each of the functional blocks is modeled in a separate alwaysblock. The state register logic is modeled as an always block, and the next-statelogic and output logic are separate always blocks, representing combinatorial logic.Because the output section can be modeled as either sensitive only to changes onstate or also sensitive to changes on inputs, you can use this to model both Mealyand Moore machines. This style is the most modular; it may take a few more linesof Verilog code, though it may be the easiest to maintain.The second style combines the next-state logic and the state register. This style is agood style to use because the next-state logic and state register are strongly related.This style is more compact than the first, and may even be more efficient becausethe next-state logic is only evaluated on clock edges, rather than whenever an inputchanges. If your state machine has many inputs that change frequently, this may bea better style to use than the first. This style has the output as a separate section soyou can use this style to model both Mealy and Moore machines.The third style leaves the state register in a separate always block, while combiningthe next-state logic and the output logic. Because the next-state logic and the outputlogic may be combinatorial, combining them still allows for modeling both Mealyand Moore machines. However, this grouping does not tend to help the readabilityof your code; styles 1 and 2 are easier to model and maintain.The fourth style combines everything into one always block. The always block issensitive only to the clock for the state register, so this implies the outputs onlychange with the state. Thus this style will only create Moore machines.172Verilog QuickstartThe fifth and final style combines the state register and output logic into one alwaysblock, so again, this only creates Moore machines.To demonstrate all these styles, with Moore and Mealy variations on them, we willuse a simple example. This example won’t be the traffic light controller, vendingmachine, or a completely trivial state machine, but instead an automatic foodcooker. This cooker has a supply of food that it can load into its heater whenrequested. The cooker then unloads the food when the cooking is done.Besides clock, the inputs to this state machine are start (which starts aload/cook/unload cycle); temp_ok (a temperature sensor that detects when the heateris done preheating); done (a signal from a timer or sensor that detects when thecooking cycle is complete); and quiet (a final input that selects if the cooker shouldbeep when the food is ready).The outputs from the machine are load (a signal that sends food into the cooker);heat (a signal that turns on the heating element, which has its a built-in temperaturecontrol); unload (a signal that removes the food from the cooker and presents it tothe diner); and beep (a signal that alerts the diner when the food is done).State Machines173Example 15-1 Style 1 Moore State Machinemodule auto_oven_style_1_moore(clock, start, temp_ok, done,quiet, load, heat, unload, beep);input clock, start, temp_ok, done, quiet;output load, heat, unload, beep;reg load, heat, unload, beep;reg [2:0] state, next_state;`define IDLE 'b000`define PREHEAT 'b001`define LOAD 'b010`define COOK 'b011`define EMPTY 'b100// State register blockalways @(posedge clock)state <= #(`REG_DELAY) next_state;// next state logicalways @(state or start or temp_ok or done) beginnext_state = state; // default to stay in current statecase (state)`IDLE: if (start) next_state=`PREHEAT;`PREHEAT: if(temp_ok) next_state = `LOAD;`LOAD: next_state = `COOK;`COOK: if (done) next_state=`EMPTY;`EMPTY: next_state = `IDLE;default: next_state = `IDLE;endcaseend// Output logicalways @(state) beginif(state == `LOAD) load = 1; else load = 0;if(state == `EMPTY) unload =1; else unload = 0;if(state == `EMPTY && quiet == 0) beep =1; else beep = 0;if(state ==`PREHEAT ||state == `LOAD ||state == `COOK) heat = 1; else heat =0;endendmoduleIn style 1, as shown in Example 15-1, each section of the state machine is modeledwith a separate always block. Style 1 can be used to represent either a Mooremachine or a Mealy machine for our automatic oven. The difference between thetwo styles is seen in the different behavior of the quiet input and beep output. Withthe Moore machine the diner must wait through the entire EMPTY state for thebeeper to be quiet. The Mealy version of this is for those diners who want the beeperto sound, and then jump up to turn it off, as shown in Example 15-2.174Verilog QuickstartExample 15-2 Style 1 Mealy State Machinemodule auto_oven_style_1_mealy(clock, start, temp_ok, done,quiet, load, heat, unload, beep);input clock, start, temp_ok, done, quiet;output load, heat, unload, beep;reg load, heat, unload, beep;reg [2:0] state, next_state;`define IDLE 'b000`define PREHEAT 'b001`define LOAD 'b010`define COOK 'b011`define EMPTY 'b100// State register blockalways @(posedge clock)state <= #(`REG_DELAY) next_state;// next state logicalways @(state or start or temp_ok or done) beginnext_state = state; // default to stay in current statecase (state)`IDLE: if (start) next_state=`PREHEAT;`PREHEAT: if(temp_ok) next_state =


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