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UCSB ECE 152A - Homework #4

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ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 1 of 9 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #4 Problem #1. A JN flip flop is constructed by (internally) complementing the K input to an otherwise normal JK flip flop. For the JN flip flop, derive the following: 1. The characteristic table 2. The characteristic equation 3. The state table 4. The state diagram 5. The excitation table Problem #2. Design a 2-bit, binary up/down counter. The counter has 2 inputs, up_down and enable. The truth table below defines the operation of the counter: enable up_down | operation 0 0 | hold count 0 1 | hold count 1 0 | decrement count 1 1 | increment count Use positive edge triggered JK flip flops. In your answer, include (1) a state diagram, (2) a state table, (3) a next state map and (4) all Kmaps used in determining flip flop inputs Problem #3. Design a three bit counter with a single input called mode. The counter counts in binary if the mode bit is zero, and counts in gray code if the mode bit is one (recall the three bit gray code is 000, 001, 011, 010, 110, 111, 101, 100). The mode bit can change at any time during the count sequence and your counter should begin counting in the new mode on the next clock input.ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 2 of 9 Design the counter using JK flip flops. You don’t have to draw the logic diagram, specifying the J and K inputs to each flip flop is sufficient. Use A, B and C as the state variable names. Include (1) a state table, (2) next state maps and (3) K-maps for all flip flop inputs. Problem #4. Consider the flip flop illustrated below: 1. Would this flip flop function as a positive (rising) or negative (falling) edge triggered flip flop (and why)? 2. Construct the characteristic table for this flip flop. 3. What modifications are necessary to transform this into a D flip flop (the output Q should take the value of the single input D after the active clock edge)? 4. What modifications are necessary to transform this into a JK flip flop (the outputs Q and Q’ should toggle after the active clock edge when A and B = 0)? 5. If all the gates have a propagation delay of 10 ns (both tPLH and tPHL), what would the worst case CLK to Q delay be? 6. Complete the timing diagram on the following page. Include arrows indicating the relationship and order of signal transitions. Assume the clock period is much greater than the gate delays. The initial conditionsECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 3 of 9 are noted on the timing diagram. Problem #5. In this problem you are to design a 3-bit counter having a single control input: x. When x is 0, the counter counts up in even numbers (0,2,4,6,0,...). When x is 1, the counter counts down in odd numbers (7,5,3,1,7,...). When the input changes, the count sequence should change appropriately from the current count. For example, if the current count is 4 and x changes from 0 to 1, the next count should be 3. If the current count is 5 and x changes from 1 to 0, the next count should be 6, etc. Implement your design using T flip flops. Note that the state diagram is the most important part of the design. Any error in the state diagram will ripple throughout the design.ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 4 of 9 Include the following: 1. A state diagram 2. A state table 3. Next state maps for the three flip flops 4. Karnaugh maps for the three T inputs 5. Simplified equations for the three T inputs Problem #6. This problem deals with the minimum clock period (or maximum frequency) of a digital system which generates a parity bit for a 3 bit data word. A parity bit is added to a data word to allow for single bit error detection and either even or odd parity can be implemented. In even parity, the total number of bits (including the parity bit) is an even number. The truth table below illustrates the generation of an even parity bit for a 3-bit data word. A B C Even Parity Bit 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 5 of 9 The block diagram for the complete digital system is given below: The parity generate block is the implementation of the combinational circuit defined in the truth table on the previous page. Based on that truth table, design the circuit using any combination of 7410’s (3 input NAND gates), 7420’s (4 input NAND gates) or 7486 (2 input XOR gates). Pinouts and switching characteristics for these devices are included on the following pages. The input and output registers are to be implemented using 7474 D flip flops. The pinout and switching characteristics for this device are also included on the following pages. The specific characteristics for the 7474 are circled (other devices are also described on this table). Include the following in your answer: 1. A Karnaugh map for the parity generate circuitry. 2. The minimized Boolean equation for the parity generate circuitry. 3. A logic diagram indicating which gates are used for the parity generate circuitry and how they are interconnected. 4. A logic diagram indicating how the 7474’s are used to implement the input and output registers. Indicate what is done with all inputs and outputs (clock, preset, clear, Q, Q’ and D). 5. A calculation of the minimum clock period necessary for your implementation to function properly. Include the equation you used to determine the minimum clock period and which numbers from the data sheet were selected and incorporated into this calculation.ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 6 of 9 7410, 7420 Switching CharacteristicsECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 7 of 9 7486 Switching Characteristics 7474 Switching CharacteristicsECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 8 of 9 Problem #7. In this problem you are to design a 3-bit counter with a single input (x). When x is 0, the count should be incremented by 1 and when x is 1, the count should be incremented by 2. Label the state variables A, B and C where A is the most significant bit. 1. Generate the state diagram for this counter. 2. Generate the state


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