Cortex-M3 Technical Reference ManualContentsList of TablesList of FiguresPrefaceAbout this bookProduct revision statusIntended audienceUsing this bookConventionsTypographicalAdditional readingARM publicationsOther publicationsFeedbackFeedback on this productFeedback on this manualIntroduction1.1 About the processor1.2 Features1.3 Interfaces1.4 Configurable options1.5 Product documentation1.5.1 Documentation1.5.2 Design Flow1.5.3 Architecture and protocol informationARM architectureBus architectureDebugEmbedded Trace Macrocell1.6 Product revisions1.6.1 Differences in functionality between r0p0 and r1p01.6.2 Differences in functionality between r1p0 and r1p11.6.3 Differences in functionality between r1p1 and r2p01.6.4 Differences in functionality between r2p0 and r2p1Functional Description2.1 About the functions2.2 Interfaces2.2.1 Bus interfacesICode memory interfaceDCode memory interfaceSystem interfacePrivate Peripheral Bus (PPB)2.2.2 ETM interface2.2.3 AHB Trace Macrocell interface2.2.4 Debug Port AHB-AP interfaceProgrammers Model3.1 About the programmers model3.2 Modes of operation and execution3.2.1 Operating modes3.2.2 Operating states3.2.3 Privileged access and user access3.3 Instruction set summary3.3.1 Cortex-M3 instructions3.3.2 Load/store timings3.3.3 Binary compatibility with other Cortex processors3.4 System address map3.4.1 Private peripheral bus3.4.2 Unaligned accesses that cross regions3.5 Write buffer3.6 Exclusive monitor3.7 Bit-banding3.7.1 Directly accessing an alias region3.7.2 Directly accessing a bit-band region3.8 Processor core register summary3.9 Exceptions3.9.1 Exception handlingBase register update in LDM and STM operationsSystem Control4.1 About system control4.2 Register summary4.3 Register descriptions4.3.1 Auxiliary Control Register, ACTLR4.3.2 CPUID Base Register, CPUID4.3.3 Auxiliary Fault Status Register, AFSRMemory Protection Unit5.1 About the MPU5.2 MPU functional description5.3 MPU programmers modelNested Vectored Interrupt Controller 6.1 About the NVIC6.2 NVIC functional description6.2.1 Low power modes6.2.2 Level versus pulse interrupts6.3 NVIC programmers model6.3.1 Interrupt Controller Type Register, ICTRDebug7.1 About debug7.1.1 Cortex-M3 ROM table identification and entries 7.1.2 System Control SpaceSCS CoreSight identification7.1.3 Debug register summary7.2 About the AHB-AP7.2.1 AHB-AP transaction types7.2.2 AHB-AP programmers modelAHB-AP Control and Status Word Register, CSW7.3 About the Flash Patch and Breakpoint Unit (FPB)7.3.1 FPB functional description7.3.2 FPB programmers modelData Watchpoint and Trace Unit8.1 About the DWT8.2 DWT functional description8.3 DWT Programmers ModelInstrumentation Trace Macrocell Unit9.1 About the ITM9.2 ITM functional description9.3 ITM programmers model9.3.1 ITM Trace Privilege Register, ITM_TPREmbedded Trace Macrocell10.1 About the ETM10.1.1 Features10.1.2 Configurable options10.2 ETM functional description10.2.1 ResourcesResource identification encoding10.2.2 Timestamp format10.2.3 Periodic synchronization10.2.4 Data and instruction address compare resources10.2.5 External inputs10.2.6 Start/stop block10.2.7 Triggering10.2.8 InterfacesRecommended CTI connections10.2.9 Operation10.3 ETM Programmers model10.3.1 Modes of operation and execution10.3.2 Register summary10.3.3 Main Control Register, ETMCR10.3.4 Configuration Code Register, ETMCCR10.3.5 System Configuration Register, ETMSCR10.3.6 TraceEnable Control 1 Register, ETMTECR110.3.7 ID Register, ETMIDR10.3.8 Configuration Code Extension Register, ETMCCER10.3.9 TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR10.3.10 Device Power-Down Status Register, ETMPDSR10.3.11 Integration Test Miscellaneous Inputs, ITMISCIN10.3.12 Integration Test Trigger Out, ITTRIGOUT10.3.13 ETM Integration Test ATB Control 2, ETM_ITATBCTR210.3.14 ETM Integration Test ATB Control 0, ETM_ITATBCTR0Trace Port Interface Unit11.1 About the Cortex-M3 TPIU11.2 TPIU functional description11.2.1 TPIU block diagrams11.2.2 TPIU Formatter11.2.3 Serial Wire Output format11.3 TPIU programmers model11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR11.3.2 Formatter and Flush Status Register, TPIU_FFSR11.3.3 Formatter and Flush Control Register, TPIU_FFCR11.3.4 TRIGGER11.3.5 Integration ETM Data11.3.6 ITATBCTR211.3.7 Integration ITM Data11.3.8 ITATBCTR011.3.9 Integration Mode Control, TPIU_ITCTRL11.3.10 TPIU_DEVID11.3.11 TPIU_DEVTYPERevisionsGlossaryCopyright © 2005-2008, 2010 ARM Limited. All rights reserved.ARM DDI 0337I (ID072410)Cortex™-M3 Revision r2p1Technical Reference ManualARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. iiID072410 Non-ConfidentialCortex-M3Technical Reference ManualCopyright © 2005-2008, 2010 ARM Limited. All rights reserved.Release InformationThe following changes have been made to this book.Proprietary NoticeWords and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous developments and improvements. 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