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Revision HistoryList of Errata1 JTAG and Serial Wire Debug2 System Control3 Hibernation Module4 Flash Controller5 GPIO6 General-Purpose Timers7 ADC8 UART9 PWM10 QEISTELLARIS ERRATAStellaris®LM3S1968 RevA2 ErrataThis document contains known errata at the time of publication for the Stellaris LM3S1968microcontroller. The table below summarizes the errata and lists the affected revisions. See thedata sheet for more details.See also the ARM® Cortex™-M3 errata, ARM publication number PR326-PRDC-009450 v2.0.Table 1. Revision HistoryDescriptionRevisionDate■ Added issue “Standard R-C network cannot be used on RST to extend POR timing” on page 6.■ Clarified issue “General-purpose timer 16-bit Edge Count or Edge Time mode does not load reloadvalue” on page 8 to include Edge-Time mode.■ Added issue “Retriggering a sample sequencer before it has completed the current sequence resultsin continuous sampling” on page 10.3.0August 2011■ Added issue “Hibernation module does not operate correctly” on page 6, replacing previousHibernation module errata items.■ Minor edits and clarifications.2.10September 2010■ Added issue “The RTRIS bit in the UARTRIS register is only set when the interrupt isenabled” on page 10.2.9July 2010■ Added issue “External reset does not reset the XTAL to PLL Translation (PLLCFG)register” on page 5.2.8June 2010■ Removed issue "Hibernation Module 4.194304-MHz oscillator supports a limited range of crystalload capacitance values" as it does not apply to this part.■ Minor edits and clarifications.2.7May 2010■ Removed issue "Writes to Hibernation module registers sometimes fail" as it does not apply to thispart.■ Added issue "Hibernation Module 4.194304-MHz oscillator supports a limited range of crystal loadcapacitance values."■ Minor edits and clarifications.2.6April 2010■ Removed issue "Setting Bit 7 in I2C Master Timer Period (I2CMTPR) register may have unexpectedresults". The data sheet description has changed such that this is no longer necessary.■ Minor edits and clarifications.2.5April 2010■ Added issue “The General-Purpose Timer match register does not function correctly in 32-bitmode” on page 8.■ Added issue "Setting Bit 7 in I2C Master Timer Period (I2CMTPR) register may have unexpectedresults".2.4February 2010■ "Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3 Debug AccessPort (DAP) is enabled" has been removed and the content added to the LM3S1968 data sheet.2.3Jan 2010Started tracking revision history.2.2Dec 20091Texas InstrumentsAugust 04, 2011/Rev. 3.0Table 2. List of ErrataRevision(s)AffectedModule AffectedErratum TitleErratumNumberA2JTAG and Serial WireDebugJTAG pins do not have internal pull-ups enabled at power-on reset1.1A2JTAG and Serial WireDebugJTAG INTEST instruction does not work1.2A2System ControlClock source incorrect when waking up from Deep-Sleep modein some configurations2.1A2System ControlPLL may not function properly at default LDO setting2.2A2System ControlI/O buffer 5-V tolerance issue2.3A2System ControlPLL Runs Fast When Using a 3.6864-MHz Crystal2.4A2System ControlExternal reset does not reset the XTAL to PLL Translation(PLLCFG) register2.5A2System ControlStandard R-C network cannot be used on RST to extend PORtiming2.6A2Hibernation ModuleHibernation module does not operate correctly3.1A2Flash ControllerMERASE bit of the FMC register does not erase the entire Flasharray4.1A2GPIOGPIO input pin latches in the Low state if pad type is open drain5.1A2GPIOGPIO pins may glitch during power supply ramp up5.2A2General-Purpose TimersGeneral-purpose timer Edge Count mode count error when timeris disabled6.1A2General-Purpose TimersGeneral-purpose timer 16-bit Edge Count or Edge Time modedoes not load reload value6.2A2General-Purpose TimersThe General-Purpose Timer match register does not functioncorrectly in 32-bit mode6.3A2ADCUse of "Always" triggering for ADC Sample Sequencer 3 does notwork7.1A2ADCIncorrect behavior with timer ADC triggering when another timeris used in 32-bit mode7.2A2ADCADC hardware averaging produces erroneous results in differentialmode7.3A2ADCRetriggering a sample sequencer before it has completed thecurrent sequence results in continuous sampling7.4A2UARTThe RTRIS bit in the UARTRIS register is only set when theinterrupt is enabled8.1A2PWMPWM pulses cannot be smaller than dead-band time9.1A2PWMPWM interrupt clear misses in some instances9.2A2PWMPWM generation is incorrect with extreme duty cycles9.3A2PWMPWMINTEN register bit does not function correctly9.4A2PWMSync of PWM does not trigger "zero" action9.5August 04, 2011/Rev. 3.0Texas Instruments2Stellaris LM3S1968 A2 ErrataRevision(s)AffectedModule AffectedErratum TitleErratumNumberA2PWMPWM "zero" action occurs when the PWM module is disabled9.6A2QEIQEI index resets position when index is disabled10.1A2QEIQEI hardware position can be wrong under certain conditions10.21 JTAG and Serial Wire Debug1.1 JTAG pins do not have internal pull-ups enabled at power-on resetDescription:Following a power-on reset, the JTAG pins TRST, TCK, TMS, TDI, and TDO (PB7 and PC[3:0]) donot have internal pull-ups enabled. Consequently, if these pins are not driven from the board, twothings may happen:■ The JTAG port may be held in reset and communication with a four-pin JTAG-based debuggermay be intermittent or impossible.■ The receivers may draw excess current.Workaround:There are a number of workarounds for this problem, varying in complexity and impact:1. Add external pull-up resistors to all of the affected pins. This workaround solves both issues ofJTAG connectivity and current consumption.2. Add an external pull-up resistor to TRST. Firmware should enable the internal pull-ups on theaffected pins by setting the appropriate PUE bits of the appropriate GPIO Pull-Up Select(GPIOPUR) registers as early in the reset handler as possible. This workaround addresses theissue of JTAG connectivity, but does not address the current consumption other than to limitthe affected period (from power-on reset to code execution).3. Pull-ups on the JTAG pins are unnecessary for code loaded via the SWD interface or via theserial boot loader. Loaded firmware should enable the internal pull-ups on the affected pins bysetting the appropriate PUE bits of the appropriate GPIOPUR registers as early in the resethandler as possible. This method does not address the current consumption other than to limitthe affected period (from


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UT EE 345L - Stellaris® LM3S1968 RevA2 Errata

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