MidtermQuestions on MidtermAdministriviaMemory and I/O busesRealistic PC architectureWhat is memory?What is I/O bus? E.g., PCICommunicating with a deviceDMA buffersExample: Network Interface CardExample: IDE disk read w. DMADriver architectureDriver architectureInterrupt driven devicesAnatomy of a diskDiskDiskDiskStorage on a magnetic platterCylinders, tracks, & sectorsDisk positioning systemSeek detailsSeek detailsSectorsSectorsDisk interfaceSCSI overviewSCSI requestsExecuting SCSI commdnsSCSI exceptions and errorsDisk performanceScheduling: FCFSScheduling: FCFSFCFS exampleShortest positioning time first (SPTF)Shortest positioning time first (SPTF)SPTF example``Elevator'' scheduling (SCAN)``Elevator'' scheduling (SCAN)CSCAN exampleVSCAN(r)Flash memoryTypes of flash memoryNAND Flash OverviewFlash Characteristics href {http://cseweb.ucsd.edu/~swanson/papers/Asplos2009Gordon.pdf}{[Caulfield]}Midterm 0 2 4 6 8 10 12 0 20 40 60 80 100"midterm.data" using 1:21/37Questions on Midterm• Problems 1–2: See David• Problem 3: See Jeremy or Samir• Problem 4: See Jeremy• Problem 5: See Jeff• Problem 6: See Andrew• Problem 7: See Samir2/37Administrivia• Recall we will have a res urrection final- Don’t panic if you didn’t do well on midterm- But make sure you understand all the answers- There may be questions on same topics on the final• Final grade based on rank and thresholds- Rank based on Projects + max(F inal, Midter m + Final/ 2)- Letter grade thresholds (“curve”) more influenced by projects• Recall: Project 3 section tomorrow3/37Memory and I/O busesI/O bus1880Mbps 1056MbpsCrossbarMemoryCPU• CPU accesses physical memo ry ove r a bus• Devices access memory over I/O bus with DMA• Devices can appear to be a region of memory4/37Realistic PC architectureAdvancedProgramableInterruptControllerbusI/OAPICCPUBridgeMainmemoryNorthbussidefront-SouthBridgebusISACPUUSBbusAGPPCIIRQsbusPCI5/37What is memory?• SRAM – Static RAM- Like two NOT gates circularly wired input-to-output- 4–6 transistors per bit, actively holds its value- Very fast, used to cache slower memory• DRAM – Dynamic RAM- A capacitor + gate, holds charge to indicate bit value- 1 transistor per bit – extremely dense storage- Charge leaks—need slow comparator to decide if bit 1 or 0- Must re-write charge after reading, and periodically refresh• VRAM – “Video RAM”- Dual ported, can write while someone else reads6/37What is I/O bus? E.g., PCI7/37Communicating with a device• Memory-mapped device registers- Certain physical addresses correspond to device registers- Load/store gets status/sends instructions – not real memory• Device memory – device may have memory OS canwrite to directly on other side of I/O bus• Special I/O instructions- Some CPUs (e.g., x86) have special I/O instructions- Like load & store, but asserts special I/O pin on CPU- OS can allow user-mode access to I/O ports with finergranularity than page• DMA – place instructions to c a rd in main memory- Typically then need to “poke” card by writing to register- Overlaps unrelated computation with moving data over(typically slower than memory) I/O bus8/37DMA buffersBufferdescriptorlistMemory buffers1001400150015001500…• Include list of buffer locations in main memory• Card reads list then acc e s s e s buffers (w. DMA)- Descriptions sometimes allow for scatter/gather I/O9/37Example: Network Interface CardHost I/O busAdaptorNetwork linkBusinterfaceLinkinterface• Link interface talks to wire/fiber/antenna- Typically does framing, link-layer CRC• FIFOs on card provide s m a ll a m o unt of buffering• Bus interface logic uses DMA to move packets to andfrom buffers in main memory10/37Example: IDE dis k re a d w. DMA11/37Driver architecture• Device driver provides seve ra l entry points to kernel- Reset, ioctl, output, interrupt, read, write, strategy . . .• How should driver synchronize w ith card?- E.g., Need to know when transmit buffers free or packets arrive- Need to know when disk request complete• One approach: Polling- Sent a packet? Loop asking card when buffer is free- Waiting to receive? Keep asking card if it has packet- Disk I/O? Keep looping until disk ready bit set• Disadvantages of polling?12/37Driver architecture• Device driver provides seve ra l entry points to kernel- Reset, ioctl, output, interrupt, read, write, strategy . . .• How should driver synchronize w ith card?- E.g., Need to know when transmit buffers free or packets arrive- Need to know when disk request complete• One approach: Polling- Sent a packet? Loop asking card when buffer is free- Waiting to receive? Keep asking card if it has packet- Disk I/O? Keep looping until disk ready bit set• Disadvantages of polling?- Can’t use CPU for anything else while polling- Or schedule poll in future and do something else, but then highlatency to receive packet or process disk block12/37Interrupt driven devices• Instead, ask card to interrupt CPU on events- Interrupt handler runs at high priority- Asks card what happened (xmit buffer free, new packet)- This is what most general-purpose OSes do• Bad under high network packet arrival rate- Packets can arrive faster than OS can process them- Interrupts are very expensive (context switch)- Interrupt handlers have high priority- In worst case, can spend 100% of time in interrupt handler andnever make any progress – receive livelock- Best: Adaptive switching between interrupts and polling• Very good for disk requests• Rest of today: Disks (network dev ice s in 1 .5 weeks)13/37Anatomy of a disk• Stack of magnetic platters- Rotate together on a central spindle @3,600-15,000 RPM- Drive speed drifts slow ly over time- Can’t predict rotational position after 100-200 revolutions• Disk arm assembly- Arms rotate around pivot, all move together- Pivot offers some resistance to linear shocks- Arms contain disk heads–one for each recording surface- Heads read and write data to platters14/37Disk15/37Disk15/37Disk15/37Storage on a magnetic platte r• Platters divided into concentric tracks• A stack of tracks o f fixed radius is a cylinder• Heads record and sense data a lo ng c y linders- Significant fractions of encoded stream for error correction• Generally only one head ac tive at a time- Disks usually have one set of read-write circuitry- Must worry about cross-talk between channels- Hard to keep mu ltiple heads exactly aligned16/37Cylinders, tracks
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