September 1993 Order Number: 231164-0058254PROGRAMMABLE INTERVAL TIMERYCompatible with All Intel and MostOther MicroprocessorsYHandles Inputs from DC to 10 MHzÐ 8 MHz 8254Ð 10 MHz 8254-2YStatus Read-Back CommandYSix Programmable Counter ModesYThree Independent 16-Bit CountersYBinary or BCD CountingYSinglea5V SupplyYAvailable in EXPRESSÐ Standard Temperature RangeThe Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcom-puter system design. It provides three independent 16-bit counters, each capable of handling clock inputs upto 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.231164–1Figure 1. 8254 Block Diagram231164–2Figure 2. Pin Configuration8254Table 1. Pin DescriptionSymbolPinType Name and FunctionNo.D7–D01–8 I/O DATA: Bi-directional three state data bus lines, connected to systemdata bus.CLK 0 9 I CLOCK 0: Clock input of Counter 0.OUT 0 10 O OUTPUT 0: Output of Counter 0.GATE 0 11 I GATE 0: Gate input of Counter 0.GND 12 GROUND: Power supply connection.VCC24 POWER:a5V power supply connection.WR 23 I WRITE CONTROL: This input is low during CPU write operations.RD 22 I READ CONTROL: This input is low during CPU read operations.CS 21 I CHIP SELECT: A low on this input enables the 8254 to respond toRD and WR signals. RD and WR are ignored otherwise.A1,A020–19 I ADDRESS: Used to select one of the three Counters or the ControlWord Register for read or write operations. Normally connected tothe system address bus.A1A0Selects0 0 Counter 00 1 Counter 11 0 Counter 21 1 Control Word RegisterCLK 2 18 I CLOCK 2: Clock input of Counter 2.OUT 2 17 O OUT 2: Output of Counter 2.GATE 2 16 I GATE 2: Gate input of Counter 2.CLK 1 15 I CLOCK 1: Clock input of Counter 1.GATE 1 14 I GATE 1: Gate input of Counter 1.OUT 1 13 O OUT 1: Output of Counter 1.FUNCTIONAL DESCRIPTIONGeneralThe 8254 is a programmable interval timer/counterdesigned for use with Intel microcomputer systems.It is a general purpose, multi-timing element that canbe treated as an array of I/O ports in the systemsoftware.The 8254 solves one of the most common problemsin any microcomputer system, the generation of ac-curate time delays under software control. Instead ofsetting up timing loops in software, the programmerconfigures the 8254 to match his requirements andprograms one of the counters for the desired delay.After the desired delay, the 8254 will interrupt theCPU. Software overhead is minimal and variablelength delays can easily be accommodated.Some of the other counter/timer functions commonto microcomputers which can be implemented withthe 8254 are:#Real time clock#Event-counter#Digital one-shot#Programmable rate generator#Square wave generator#Binary rate multiplier#Complex waveform generator#Complex motor controllerBlock DiagramDATA BUS BUFFERThis 3-state, bi-directional, 8-bit buffer is used to in-terface the 8254 to the system bus (see Figure 3).28254231164–3Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic FunctionsREAD/WRITE LOGICThe Read/Write Logic accepts inputs from the sys-tem bus and generates control signals for the otherfunctional blocks of the 8254. A1and A0select oneof the three counters or the Control Word Registerto be read from/written into. A ‘‘low’’ on the RDin-put tells the 8254 that the CPU is reading one of thecounters. A ‘‘low’’ on the WRinput tells the 8254that the CPU is writing either a Control Word or aninitial count. Both RDand WR are qualified by CS;RDand WR are ignored unless the 8254 has beenselected by holding CSlow.CONTROL WORD REGISTERThe Control Word Register (see Figure 4) is selectedby the Read/Write Logic when A1,A0e11. If theCPU then does a write operation to the 8254, thedata is stored in the Control Word Register and isinterpreted as a Control Word used to define theoperation of the Counters.The Control Word Register can only be written to;status information is available with the Read-BackCommand.COUNTER 0, COUNTER 1, COUNTER 2These three functional blocks are identical in opera-tion, so only a single Counter will be described. Theinternal block diagram of a single counter is shownin Figure 5.The Counters are fully independent. Each Countermay operate in a different Mode.The Control Word Register is shown in the figure; itis not part of the Counter itself, but its contents de-termine how the Counter operates.The status register, shown in Figure 5, whenlatched, contains the current contents of the ControlWord Register and status of the output and nullcount flag. (See detailed explanation of the Read-Back command.)The actual counter is labelled CE (for ‘‘Counting Ele-ment’’). It is a 16-bit presettable synchronous downcounter.OLMand OLLare two 8-bit latches. OL stands for‘‘Output Latch’’; the subscripts M and L stand for‘‘Most significant byte’’ and ‘‘Least significant byte’’38254231164–4Figure 4. Block Diagram Showing Control Word Register and Counter Functions231164–5Figure 5. Internal Block Diagram of a Counter48254respectively. Both are normally referred to as oneunit and called just OL. These latches normally ‘‘fol-low’’ the CE, but if a suitable Counter Latch Com-mand is sent to the 8254, the latches ‘‘latch’’ thepresent count until read by the CPU and then returnto ‘‘following’’ the CE. One latch at a time is enabledby the counter’s Control Logic to drive the internalbus. This is how the 16-bit Counter communicatesover the 8-bit internal bus. Note that the CE itselfcannot be read; whenever you read the count, it isthe OL that is being read.Similarly, there are two 8-bit registers called CRMand CRL(for ‘‘Count Register’’). Both are normallyreferred to as one unit and called just CR. When anew count is written to the Counter, the count isstored in the CR and later transferred to the CE. TheControl Logic allows one register at a time to beloaded from the internal bus. Both bytes are trans-ferred to the CE simultaneously. CRMand CRLarecleared when the Counter is programmed. In thisway, if the Counter has been programmed for onebyte counts (either most significant byte only or leastsignificant byte only) the other byte will be zero.Note that the CE cannot be written into; whenever acount is written, it is written into the CR.The Control Logic is also shown in the diagram.CLK n, GATE n, and OUT n are all
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