ECE 551 Digital System Design Synthesis Lecture 2 Pragmatic Design Issues Part 2 Overview Miscellaneous problems that arise in design and their solutions Issues considered in this part o Asynchronous Circuits o Clock Design and Delays o Electrical Issues 9 6 2001 ECE 551 Fall 2001 1 Asynchronous Circuits Delay dependent design Combinational hazards Level pulse conversion Synchronization Memory timing 9 6 2001 ECE 551 Fall 2001 2 Delay Dependent Design A DA A A A DA 9 6 2001 ECE 551 Fall 2001 3 Combinational Hazards Hazard 1 in a Multiplexer A B 1 F C B F 9 6 2001 ECE 551 Fall 2001 4 Combinational Hazards continued Classification of Combinational Hazards o Static o Dynamic o Essential Consequences of Hazards o Signals with hazards in or entering asynchronous environments Hazard Prevention o Redundant Logic o Delay Control 9 6 2001 ECE 551 Fall 2001 5 Level Pulse Conversion DATA IN DATA OUT D Clock C Q Level on DATA IN must be longer than a clock period and must not rise close to the positive clock edge Ideally synchronous with the Clock 9 6 2001 ECE 551 Fall 2001 6 Synchronization D Clock D Q Q Clock C Req C Rep Asynchronous Rep can cause sequential circuit malfunction since it reaches two or more flip flops Solution Put synchronizer PET DFF in Rep path 9 6 2001 ECE 551 Fall 2001 7 Metastability A specific phenomena that in the present of certain closely timed events on the inputs can cause bizarre latch and flip flop behavior o Hanging for a time at a threshold level o Produce a damped oscillation One remedy Use two to three synchronizers in series 9 6 2001 ECE 551 Fall 2001 8 Memory Timing Many memories are asynchronous circuits e g SRAMs are latch based without a clock on the latch o Their inputs can respond to glitches such as hazards o A majority of all memory inputs need to be glitch free Since memories involve capture of data in selectivelyaddressed cells set up and hold times apply to many of the inputs notably the addresses Memory outputs often involve 3 state buses one must be sure that the bus is active whenever data is being read When designing with memories careful attention must be given to meeting fully all of the timing specifications 9 6 2001 ECE 551 Fall 2001 9 Asynchronous Design Using classical techniques because of the difficulty of eliminating the hazards very difficult to insure correct operation under all timing possibilities Therefore don t do it If you truly need it investigate some of the more contemporary approaches which avoid some of the many difficulty 9 6 2001 ECE 551 Fall 2001 10 Clocking Design Clock skew Clock gating Clock jitter Clock buffers Interconnect delay control 9 6 2001 ECE 551 Fall 2001 11 Clock Skew Clock skew is the arrival of the active clock edge s at different times in different parts of a chip or system Clock skew can result from o logic delays as in clock gating and buffering o interconnection delays Clock skew can cause o Premature capture of new state values o The shortening of the effective allowable delay along a path from flip flop to flip flop o Lengthening of the effective allowable delay along a path from flip flop to flip flop 9 6 2001 ECE 551 Fall 2001 12 Clock Gating Use of gate logic to interrupt the clock signal to a portion of the logic to prevent the state from changing Why use it o Simplifies logic o Reduces power consumption Why not use it o Can circuit failure due to clock skew o Complicates circuit testing 9 6 2001 ECE 551 Fall 2001 13 Clock Jitter Clock does not provide a signal having a fixed frequency Clock period is o slightly shorter or o slightly longer on any given cycle The clock jitter is the absolute value of the maximum difference between o the nominal period and o the shortest and the longest clock periods Can be very serious if circuit has multiple clocks with independent jitter 9 6 2001 ECE 551 Fall 2001 14 Combinational Logic Delay Upper Bound Components of the Bounds o o o o Nominal Clock Period CP FF Propagation Delay tFF FF Set up Time tSU Clock skew of destination FF clock with respect to source FF clock or tsc o Clock Jitter Magnitude tCJ Combinational Logic Delay Upper Bound along Particular FF to FF path o DCL CP tsc tCJ tFF tSU From this equation we see that o Clock jitter degrades performance o Clock skew may either degrade if negative or enhance if positive performance 9 6 2001 ECE 551 Fall 2001 15 Combinational Logic Delay Lower Bound Related to incorrect function due to hold time violation Left as an exercise 9 6 2001 ECE 551 Fall 2001 16 Clock Buffers Reasons for buffering o Large driven load o Long clock interconnects Must be designed to minimize skew Overall clock distribution in an aggressive design is a major separate task 9 6 2001 ECE 551 Fall 2001 17 Interconnect Delay Control Interconnect delay exclusive of clocks for global interconnects is a significant component of the FF to FF delay in submicron channel length circuits Implication Interconnect delay has a significant impact on performance in submicron channel length designs o Ideally global routes are from FF to FF o If combinational logic involved all interconnect delay subtracted from combinational logic delay upper bound 9 6 2001 ECE 551 Fall 2001 18 Interconnect Delay Control continued Methods of handling interconnect delay o Chip floorplanning to reduce global routing o Interconnect driver strength and inserted buffers o Interconnect sizing o Circuit retiming if combinational logic in series with global interconnect o Last resort addition of FFs to very troublesome paths and redesign of parts of system affected 9 6 2001 ECE 551 Fall 2001 19 Electrical Issues Loading Constant inputs Slew rate and ground bounce 9 6 2001 ECE 551 Fall 2001 20 Loading The loading of a gate or other component can affect o Output levels o Local Power Dissipation o Delay Consider two logic families assuming both loads and drivers are in the families o TTL o CMOS 9 6 2001 ECE 551 Fall 2001 21 Loading of TTL Gates TTL Transistor Transistor Logic is a current sinking technology For driven TTL gates at LOW a substantial current flows out of inputs into the driving output The static current for the driving gate at LOW o IC VCC RC RB FO where RC is the output resistance of the TTL driver transistor in saturation RB is the resistance in the driven gates governing the input current and FO is the fanout in terms of number of gates driven 9 6 2001 ECE 551 Fall 2001 22 Loading of TTL Gates As FO increases the current increases which increases o the