ECE 551 Digital Design And Synthesis Week 01 Course Introduction Review Introduction to Verilog Administrative Minutiae Instructor TA Enrollment Classroom Exam Time polls up on Learn UW until next Friday Please complete it Homework 1 posted soon CAE Account and CSL Linux Tutorials 2 Overview About this class Overview of Hardware Description Languages HDLs and their role in hardware design Hardware implementations overview Quick Review Introduction to Verilog Combinational Logic Finite State Machines 3 Course Purpose Provide knowledge and experience in Teach you to be able to think hardware Contemporary logic design using an HDL Verilog HDL testbench design and simulation Synthesis and verification Analysis of design tradeoffs Optimizing hardware designs Design tools commonly used in industry 4 What You Should Already Know Principles of basic digital logic design ECE 352 Number representations Boolean algebra Gate level design K Map minimization Sequential logic design Finite State Machines Basic arithmetic combinational logic structures If haven t taken an equivalent course contact me ASAP How to log in to CAE Linux machines We will be using software in EH B555 throughout this course 5 Course Information Lecture 11 00am 11 50am MWF 2534 EH Discussion TBA Instructor office hours Michael Morrow E mail morrow engr wisc edu Office Hours http morrow ece wisc edu schedule htm TA office hours Arslan Zulfiqar E mail zulfiqar wisc edu Office Hours TBA 6 Course Website http morrow ece wisc edu ECE551 Learn UW https learnuw wisc edu Check them frequently Syllabus Course updates Lecture slides Homework assignments Project information Supplemental readings Tutorials Gradebook 7 Course Materials Lectures Presented in class Text Optional S Palnitkar Verilog HDL A Guide to Digital Design and Synthesis 2nd Ed Standards IEEE Std 1364 2001 IEEE Standard Verilog Hardware Description Language IEEE Inc 2001 IEEE Std 1364 1 2002 IEEE Standard for Verilog Register Transfer Level Synthesis IEEE Inc 2002 Synopsys on line documentation Other useful readings posted on Learn UW 8 Evaluation and Grading Approximately 30 Homework 35 Project group of two or three students 35 Exams two exams during semester and an optional final exam Optional Final Exam can be used to improve exam score 9 Homework Assignments are to be completed individually unless otherwise stated Homework is due at the beginning of class Homework 1 posted soon 10 penalty for each late period of 24 hours Not accepted 72 hours after deadline Your responsibility to get HW to instructor or TA Due 9 XX 10 Class Project Work in groups of 2 or 3 students Design model simulate synthesize and test a complex digital system Several milestones Forming teams Project status report Out of class demonstrations Project final report More details coming later in the course Start thinking about potential partners within the next few weeks 11 Course Tools Industry standard design tools Tutorials will be available for both tools Software is available in B555 Lab ModelSim HDL Simulation Tools MentorGraphics Design Vision Synthesis Tools Synopsys G Plus 40 45 nm Standard Cell Library TSMC ModelSim tutorial part of HW1 Design Vision tutorial a few weeks later Can work though tutorials on your own 12 What you will get from this class This class will teach you how to use Hardware Description Languages HDLs to design verify and validate digital logic You will learn how to synthesize HDLs into hardware using the same tools used in industry You will participate in the always enlightening process of working to design a digital system in a team environment By the end of this course most of you should be qualified for an entry level job or internship at a hardware design firm 13 Overview About this class Overview of HDLs and their role in hardware design Hardware implementation overview Quick Review Introduction to Verilog Combinational Logic Finite State Machines 14 15 16 HDL Overview Hardware description languages HDLs Textual descriptions of digital logic Description languages not Programming languages Allow modeling and simulating the functional behavior and timing of digital hardware Synthesis tools take an HDL description and generate a technology specific netlist real hardware representation Two main HDLs used by industry Verilog C based industry driven VHDL Ada based defense industry university driven Other options available BlueSpec SystemC 17 Describing Hardware not Software Hardware is created during synthesis Even if a is true still if a f c d else if b f d else f d e performs d e HDLs are inherently parallel Learn to understand how descriptions translated to hardware c f d e b a 18 OK but why not just use Schematic Capture 19 Why Use an HDL More and more transistors can fit on a chip Allows larger designs Work at transistor gate level for large designs extremely difficult and extremely expensive Many designs need to go to production quickly Abstract large hardware designs BIG CAVEAT Describe what you need the hardware to do Tools then design the hardware for you Good descriptions Good hardware Bad descriptions BAD hardware 20 Why Use an HDL Simplified faster design process Explore larger solution space Smaller faster lower power Throughput vs latency Examine more design tradeoffs Lessen the time spent debugging the design Design errors still possible but in fewer places Generally easier to find and fix Can reuse design to target different technologies Don t manually change all transistors for rule change 21 Other Important HDL Features Are highly portable text Are self documenting when commented well Describe multiple levels of abstraction Represent parallelism Provides many descriptive styles Serve as input for synthesis tools Structural Register Transfer Level RTL Behavioral 22 HDL Overview HDLs may LOOK like software but they re not NOT a program Doesn t run on anything Though we do simulate them on computers This is an important distinction to remember Also use HDLs to test the hardware you create Some special HDL code can be used more like software but is only for simulation purposes not for synthesis 23 HDL Dichotomy Sim VS Synth HDL code can be divided into two major categories Synthesizable Code Can be converted into real hardware Bound by the same limitations as hardware Can be both simulated and synthesized Non Synthesizable Code Only meant for simulation Can represent behaviors that are too difficult or too expensive to create in real hardware Used