ECE 551 Homework 1 Michelle Joy Moravan February 10 2006 Michelle Joy Moravan ECE 551 Homework 1 February 10 2006 1 Give the following numbers in Verilog notation a Decimal 28 in binary digits 10 bits 10 b11100 b Octal 37 in decimal digits 6 bits 6 d31 c Decimal 42 in hex digits 11 bits 11h 2a 2 Write the following Verilog vector declarations a Input variable A 3 bits wide rightmost bit with highest index leftmost bit at index 0 input A 0 2 b Output variable X 5 bits wide leftmost bit with highest index rightmost bit at index 2 output X 6 2 3 Complete the Modelsim tutorial I have completed the Modelsim tutorial If I had any problems with it I discussed them with the TA either in person or through email The corresponding waveform appears in Figure 1 Michelle Joy Moravan ECE 551 Homework 1 February 10 2006 sim c1 state sim c1 sub0 lsb 000000000 sim c1 sub0 00000000 sim c1 sub1 00000000 00201050 sim c1 sub2 00000000 00483052 sim c1 sub3 00000000 sim c1 word line buf 00 00101000 001100010 000111011 000000000 001100010 000111011 000000000 001100010 000111011 000000000 00201062 0000003b 00101000 00201062 0000003b 00101000 00201062 0000003b 00101000 00201050 00000000 00000000 00183071 00284001 00000000 003030a3 00000000 01 00000000 012870d3 00201050 00284001 0000003b 00201050 00284001 0000003b 0000003b 00483052 003030a3 0000003b 00483052 003030a3 0000003b 00483052 0000003b 00183071 012870d3 0000003b 00183071 012870d3 0000003b 00183071 0000003b 00000000 01 01 Top Level sim uut ce sim uut zero sim uut ofl sim uut ip en sim uut ip jo sim uut we sim uut r sel sim uut l valid sim uut alu code 0 2 1 2 1 3 1 0 2 1 2 1 3 1 0 2 1 2 1 3 1 0 2 1 sim uut alu amt 00000 sim uut rd a 0 sim uut rd b 0 sim uut wr 0 sim uut ip 00000000 sim uut imm 00000000 2 3 1 2 1 3 00000001 00000001 0 00000002 00000001 0 5 6 0 2 4 3 1 4 5 6 7 00000003 00000001 00000004 00000005 00000001 00000006 00000007 3 2 1 3 00000008 00000001 00000000 00000000 00000001 00000001 00000002 00000001 400 0 5 6 0 2 4 3 1 4 5 6 7 00000003 00000001 00000004 00000005 00000006 00000001 800 Entity t proc Architecture Date Thu Jan 26 23 31 46 CST 2006 Row 1 Page 1 Figure 1 Tutorial Waveform 4 Create a structural description of the following logic equations module wire wire wire problem4 output x y input a b c d not b not c not d x1 x2 x3 y1 y2 y3 not not b b not not c c not not d d and x1 a not b and x2 not b not c and x3 a c not d and y1 a b and y2 b c and y3 a c or x x1 x2 x3 00000007 3 2 1 3 00000008 00000001 00000000 00000000 00000001 00000001 00000002 00000001 0 5 6 0 2 4 3 1 4 5 6 7 00000003 00000001 00000004 00000005 00000006 00000001 1200 00000007 3 2 1 3 00000008 00000001 00000000 00000000 00000001 00000001 00000002 00000001 00000003 00000001 Michelle Joy Moravan ECE 551 Homework 1 or y y1 y2 y3 endmodule timescale 1ns 1ns module t problem4 reg 4 0 stim wire xout yout problem4 m1 xout yout stim 3 stim 2 stim 1 stim 0 initial monitor t x b y b a b b b c b d b time xout yout stim 3 stim 2 stim 1 stim 0 initial 150 finish initial begin for stim 0 stim 16 stim stim 1 begin 5 end end endmodule Here is the monitor output run 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 x 1 x 1 x 0 x 0 x 0 x 0 x 0 x 0 x 1 x 1 x 1 x 1 x 0 x 0 x 1 x 0 x 1 y 0 y 0 y 0 y 0 y 0 y 0 y 1 y 1 y 0 y 0 y 1 y 1 y 1 y 1 y 1 y 1 y 0 a 0 a 0 a 0 a 0 a 0 a 0 a 0 a 0 a 1 a 1 a 1 a 1 a 1 a 1 a 1 a 1 a 0 b 0 b 0 b 0 b 0 b 1 b 1 b 1 b 1 b 0 b 0 b 0 b 0 b 1 b 1 b 1 b 1 b 0 The corresponding waveform appears in Figure 2 c 0 c 0 c 1 c 1 c 0 c 0 c 1 c 1 c 0 c 0 c 1 c 1 c 0 c 0 c 1 c 1 c 0 d 0 d 1 d 0 d 1 d 0 d 1 d 0 d 1 d 0 d 1 d 0 d 1 d 0 d 1 d 0 d 1 d 0 February 10 2006 Michelle Joy Moravan ECE 551 Homework 1 February 10 2006 inputs t problem4 stim 3 t problem4 stim 2 t problem4 stim 1 t problem4 stim 0 outputs t problem4 xout t problem4 yout 0 20 40 Entity t problem4 Architecture Date Sun Jan 29 15 56 22 CST 2006 Row 1 Page 1 Figure 2 Problem 4 Waveform 5 Structurally implement a gray code counter module comb gray code output 2 0 out input 2 0 in wire 2 0 not in wire x2a x2b x1b x1a x0a x0b not not in 2 in 2 not not in 1 in 1 not not in 0 in 0 and x2a in 0 in 2 and x2b x1b not in 0 in 1 and x1a in 0 not in 2 and x0a not in 1 not in 2 and x0b in 1 in 2 or out 2 x2a x2b x1b or out 1 x1a x2b x1b or out 0 x0a x0b 60 80 Michelle Joy Moravan ECE 551 Homework 1 endmodule module problem5 output 2 0 out input clk rst wire 2 0 next state comb gray code cgc next state out dff dff2 out 2 next state 2 clk rst dff dff1 out 1 next state 1 clk rst dff dff0 out 0 next state 0 clk rst endmodule module t problem5 wire 2 0 out reg clk rst problem5 gray counter out clk rst initial monitor t out b rst b time out rst initial 500 finish initial begin clk 0 forever 5 clk clk end initial begin rst 1 10 rst 0 end endmodule Here is the monitor output run 90 0 5 10 15 25 35 45 55 65 75 85 out xxx out 000 out 000 out 001 out 011 out 010 out 110 out 111 out 101 out 100 out 000 rst 1 rst 1 rst 0 rst 0 rst 0 rst 0 rst 0 rst 0 rst 0 rst 0 rst 0 The corresponding waveform appears in Figure 3 February 10 2006 Michelle Joy Moravan ECE …