Fall 21 Lecture 2 Commenting Meta stability Verilog Syntax literals 4 value strength vectors Dataflow Verilog Handy Miscellaneous Administrative Matters Tutorial sessions Tuesday 6 30 8 00 for those in Dis 302 only in B555 Linux lab Wednesday 6 30 8 00 on General channel of MS Teams Wednesday 8 00 9 30 on General channel of MS Teams Can also do on your own If you are a windows user install ModelSim locally OR look at video on how to remote to Unix Watch Videos on mid final sections of Lecture02 Quiz on these lectures next Monday in class Homework 1 Due Next week by beginning of class 2 Comments in Verilog Commenting is important In industry many other poor schmucks are going to read your code Some poor schmuck perhaps you 4 years later are going to have to reference your code when a customer discovers a bug The best comments document why you are doing what you are doing not what you are doing Any moron who knows verilog can tell what the code is doing that thing Commenting in Verilog always posedge clk begin end Sig FF1 Sig Sig FF2 Sig FF1 Sig FF3 Sig FF2 Capture value of Sig Line in FF Flop Sig FF1 to form Sig FF2 Flop Sig FF2 to form Sig FF3 start bit is Sig FF2 Sig FF3 assign start bit Sig FF2 Sig FF3 1 b1 1 b0 Read with sarcasm Comment why motivation thought process you are doing Thanks for the commenting the code pal It tells me so much more than the verilog itself 3 4 1 3 2 4 1 Consequence of Bad Commenting Commenting in Verilog Sig start bit clk clk clk The code synthesizes as shown above Being the next arrogant engineer reading the code and the comments I realize there is an optimization to be made There is no need for the two flops up front So I delete them always posedge clk Sig is asynchronous and has to be double flopped for meta stability reasons prior to use begin Sig FF1 Sig Sig FF2 Sig FF1 double flopped meta stability free Sig FF3 Sig FF2 flop again for use in edge detection end Start bit in protocol initiated by falling edge of Sig line assign start bit Sig FF2 Sig FF3 1 b1 1 b0 Can see 2 types of comments Comment to end of line is Multi line comment starts with and ends with This is better commenting It tells you why stuff was done 6 5 7 6 8 Aside what is meta stability Back to back inverters Form a memory loop that is central to latch D 1 0 Q D 0 1 Q E 0 E 0 D 0 1 0 1 Q E 1 weak Aside what is meta stability VDD 2 1 0 D VDD 2 Q E 1 0 asynchSig clk clk clk Vout vs Vin inverter Vout 1 2V 0 6V 0 6V 1 2V Vin Yes the first flop can go meta stable but can is stay in that state for a whole clock period Yes and a meteor could crash through the roof and kill us all Take away Always double flop asynch signals before using them 8 2 5 7 Numbers in Verilog General format is size base number Examples 4 b1101 this is a 4 bit binary number equal to 13 10 h2e7 this is a 10 bit wide number specified in hex Available bases d decimal please only use in test benches h hex use this frequently b binary use this frequently for smaller s o octal who thinks in octal please avoid Numbers in Verilog Numbers can have x or z characters as values x unknown z High Impedance 12 h13x 12 bit number with lower 4 bits unknown If size is not specified then it depends on simulator machine Always size the number for the DUT verilog Why create 32 bit register if you only need 5 bits May cause compilation errors on some compilers Supports negative numbers as well 16 h3A I rarely if ever use this I prefer to work 2 s complement directly this would be 3A in hex i e FFC6 in 2 s complement 9 10 Identifiers Signal Names Identifiers are the names you choose for your signals In a programming language you should choose descriptive variable names In a HDL you should choose descriptive signal names Use mixed case and or to delimit descriptive names assign parityErr serial reg nxtState returnRegister Have a convention for signals that are active low Many errors occur on the interface between blocks written by 2 different people One assumed a signal was active low and the other assumed it was active high I use n at the end of a signal to indicate active low rst n 1 b0 assert reset Signal Values Strength in Verilog Signals can have 1 of 4 values Need high impedance for modeling of tri state busses 0 1 x z Value Meaning Logic zero false condition Logic one true condition Unknown either uninitialized or in contention High impedance Not driven or not connected EEPROM 16 16 d CPU clk rd eep 0 5 1 s u b d rd ram q What value does q have prior to any positive clock edge RAM 16 16 It is unknown x uninitialized 11 12 9 11 10 12 3 Resolving 4 Value Logic A B A OUT OUT A B A B OUT 0 0 0 0 1 1 1 1 1 0 x X 0 z X 1 x 1 1 z 1 A B OUT 0 0 0 0 1 0 1 1 1 0 x 0 0 z 0 1 x x 1 z x OUT A OUT 0 1 x z 1 0 x X S T OUT A B S A T B OUT 0 0 z z 0 1 z x 0 x z 1 0 z z 0 1 0 0 1 1 0 0 z 1 1 1 z 1 x x z 1 z x 0 z x 1 0 x 0 1 x x Signal Values Strength in Verilog Strength Level Meaning supply strong pull weak highz Strongest like a supply VDD or VSS Strong default if not specified Medium strength like a pullup device Weak like a keeper sustainer leaker High impedance Concept of drive strength supported to model certain CMOS circuits that utilize contention D inv1 Q E inv2 not inv1 Q n1 not weak0 weak1 inv2 n1 Q 13 14 reg or logic in Verilog reg or logic are storage nodes They retain their value till a new value is assigned Unlike a net wire they do not need a driver Can be changed in simulation by assigning a new value Signals of type reg are not necessarily FlipFlops Anything assigned in an always or initial block must be assigned to a signal of type reg or logic This inconsistency along with people s inability to keep it straight was part of the motivation for creation of the superset type logic Just make you life easier by using …