EE 321 Lab 8 Fall 2003EE321 – Lab 8MOS Field Effect Transistors (MOSFET’s), Part IThe purpose of this lab is to investigate the characteristics of MOSFET’s, and to use them insome simple circuits. For simplicity we will use only n-channel devices.Static Characteristics1. The CMOS CD4007 integrated circuit contains six enhancement MOSFET’s, three n-channeland three p-channel. (See the CD4007 datasheet. for its specs.) The n-channel bodies (p-silicon) are connected to pin 7 and must be kept at the most negative voltage used in thecircuit. The p-channel bodies (n-silicon) are connected to pin 14 and must be kept at themost positive voltage used in the circuit. The drain and source are interchangeable on Q2(p-channel MOSFET, pins 1, 2 and 3) and Q5 (n-channel MOSFET, pins 4, 5 and 3).Figure 1.• WARNING! Although there are protection diodes connected to the input pins to min-imize damage from static charge, Two outputs are not protected. Anti-staticprecautions must be taken. Be very careful. Use wrist strap when handling andinserting into the board. Make sure all connections are correct before turning on thepower. Ground all unused inputs. Keep your chip in the static bag when not in use. Donot change connections with power on. Connect pins 7 and 14 to the correct voltages.• In this lab we will use a different method to isolate a signal from ground. In another labwe used an isolation transformer to “float” the signal generator. This creates a potentialfor a dangerous condition since the case of the signal generator is not grounded. Ifconnected properly and with properly working equipment there is not a danger. Inthis lab we will use a small signal transformer to isolate the ground of the signal whilekeeping the case of the signal generator grounded and safe. The primary, P, side of thetransformer should be c onnected to the signal generator (if there is a center tap it shouldbe used to increase the output level).• Build the circuit in Figure 2 and set the inputs to meas ure iDand vDSin the saturationregion for one of the n-channel devices (Q5, pins 3, 4, 5) using the circuit shown. Withthe gate voltage set to about 5 V, adjust the signal generator to a triangle wave withmaximum amplitude at 1 kHZ. Be sure to connect pin 7 to ground and pin 14 to +15 V.iDis proportional to the negative of the voltage across the 100 Ω resistor, ch 2 inverted.Ch 1 is vDS. Now change the gate voltage to control current flowing in the MOSFET.1EE 321 Lab 8 Fall 2003+15VPin 5Pin 4Pin 7100100k10kGenSigPin 14Pin 3Ch 2Ch 1Figure 2.• Display iDvs. vDSfor the n-Channel FET. The curves should be similar to the curvesin Sedra and Smith Figure 4.16.• Measure Vtby varying the gate voltage until current just begins to flow in the draincircuit (increase the sensitivity of the scop e to get a good measurement).• Carefully draw the characteristics this transistors at four values of vGS. Label youraxes. One axis should be iDin mA.• Find k0nW/L from one these curves in the saturation region.2. The MOSFET behave as a variable resistor for SMALL drain-source voltages (both positiveand negative vDS) See Figure 4.4 in Sedra and Smith.• Decrease the signal amplitude.• Find the resistance (from your measurements of the slope with average vDS= 0 i.e. nooffset) of the MOSFET for small vDSvalues when vGS= Vt+ 1. Compare with theory(Sedra and Smith eq. 4.13).• Find the resistance for vGS= 0 V and 15 V.Voltage Controlled Switch3. Construct the ”chopper” circuit of Figure 3, which uses a square wave across the gate-sourceto turn the MOSFET on and off. The path from the drain to source acts as a resistor in asimple voltage divider. The resistance is very high for off and low for on.• Note that pin 7 must be connected to -5 V so that vican go negative.• Set vito a 2V p-p sin at 1 kHz and vchopto a square wave from -10 to +10 V at 100 Hz.Sketch or copy the output.• Change vchopto 10 kHz and sketch or copy the output.vi+15Vvo47k100kvchopPin 3Pin 5Pin 7−5VPin 4Pin 142EE 321 Lab 8 Fall 2003Figure 3.Variable Gain Amplifier4. The gain of an op-amp amplifier circuit can be controlled by using a MOSFET as a variablegain-setting resistor. The resistance of the MOSFET can be varied by changing the gatevoltage on the FET. Construct the circuit in Figure 4 and apply a small input voltage (lessthan 50 mV p-p) at 1 kHz. How much can the gain be varied, and does this agree with therange of resistance values for the FET?−5V10k100k10kvivoPin 14+15VPin 5 Pin 4Pin 7LF411Pin 3Figure 4.5. With the gain of the amplifier at approximately 5, increase the input s ignal amplitude untilthe output distorts noticeably. What causes the distortion? Sketch a distorted waveform.6. The distortion can be reduced dramatically by feeding half of the drain voltage back to thegate with Rf, as shown in Figure 5. Connect a 1 V p-p sine wave as shown to vary the gatevoltage. Increase the input signal amplitude until the output distorts noticeably. Is there animprovement?−5V100k 10k100k10kvivoPin 14+15VPin 5 Pin 4Pin 7LF411Pin 3RfFigure 5.3EE 321 Lab 8 Fall 2003Pre-Lab1. What is the purpose of the diode in Figure 2? OR Why don’t we want a negative voltage atpin 4?2. If Vtis known, how would you find k0nW/L from the measurement of the drain current insaturation?3. Find the output voof the circuit in Figure 4 as a function of viand vGS. Assume the FET is inthe triode region and its current is determined by vGSand vDS. That current will determinevo. Show that, if viis small, the output depends only of vi.4. Find the output voof the circuit in Figure 5 as a function of viand