EE 321 Analog Electronics, Fall 2010Exam 3 November 17, 2010Rules: This is a closed-book exam. You may use one small note card previously preparedand the attached formula sheet. The exam will last 50 minutes. Each problem counts equallytoward your grade. IMPORTANT: Use symbolic math or loose points: name theresistors and voltages using the usual terminology and only insert numericalvalues at the end.1. NPN Single-stage amplifier. For this circuit give the three terminal voltagesand the three terminal currents. Assume β = 100. Draw a small-signal model.What is the gain Avo? If a signal, vsig, with output resistance 1 kΩ is attachedto the input and a 10 kΩ resist or is attached to the output, what is the overallgain, vo/vsig?+15 V8K1.5MOutInTerminal voltages and currents:It is easy to see that VE= 0 and VB= VBE= 0.7 V.IB=VCC− VBERB=15 − 0.71.5= 9.5 µAThen, assuming active mode, IC= βIB= 0.95 mA and IE= 0.96 mA. VC= VCC− ICRC=15 − 8 × 0.96 = 7.37 V.Small-signal model:sigvRsigRBrpiRCRLvivoIncluding the signal generator and lo ad resistor.Open-circuit gain Avo:Avo= −gmRc= −0.0384 × 8 × 103= −307where gm=ICVT=0.9625= 0.0384 Ω−1Gain, Gv:Gv= −RB||rπRsig+ RB||rπgm(RC||RL)where rπ=βgm=1000.0384= 2.6 kΩ, and RB||rπ= 2.6 kΩ. ThenGv= −2.61 + 2.6× 0.0384 × (8||10) × 103= 1232. PNP single-stage amplifier. For t his circuit give the three terminal voltagesand the three terminal currents. Assume β = 100. What is the gain Avo? If asignal, vsig, with output resistance 1 kΩ is attached to the input, and the outputis open, w hat is the overall voltage gain, vo/vsig? Use quick approximations forboth gain and input resistance or you will run out of time.+15 V1K2K13K7KThe current into the base is small compared to the current in the base biase voltag e dividerso we ignore the base current and getVB= VCCR2R1+ R2= 15 ×132 + 13= 13 VThen VE= VB+ VEB= 13 + 0.7 = 13.7 V. ThenIE=VCC− VERE=15 − 13.71= 1.3 mAThen IB=IEβ+1=1.3101= 13 µA and IC= αIE=100101× 1.3 = 1.29 mA, and thenVE= IERE= 1.29 × 7 = 9 VThe open-circuit gain isAvo= −RCRE= −71= −7The overall gain is Avomultiplied by the voltage division between the input and signalresistance. The input resistance is roughly equal to the smallest base bias resistors, Rin=2 kΩ. ThenGvo= AvoRinRsig+ Rin= −7 ×21 + 2= −4.73. Biasing. D er ive the expressions for ICand for IEfor this c ir cuit. What makesthis a bet ter circuit for obtaining a particular value of ICthan the circuit inquestion 1?VCCCRBRWe see that the current through RCis IEand can wirteVCC= IERC+IEβ + 1RB+ VBEIE=VCC− VBERC+RBβ+1andIC= αIE= αVCC− VBERC+RBβ+1The circuit is better at biasing ICand IE, because there is a weaker dependence on bothVBEand β than the circuit in question 1. The circuit in question 1 has a linear dependenceon β.4. DC analysis. For these circuits give the three terminal voltages and the threeterminal currents, and state t he operating mode. Assume β = 100 for all.+15 V1K 1K+15 V1K100K+15 V−15 V1K100KFor the first circuit it is is active mode because the bias cannot be at a lower voltage thanthe collector. We have VC= 0 V, andIBRB+ VEB+ (β + 1) IBRE= VEEIB=VEE− VEBRB+ (β + 1) RE=15 − 0.7100 + 101= 71 µAIE= (β + 1) IB= 101 × 0.071 = 7.2 mAIC= βIB= 7.1 mAVB= IBRB= 100 × 0.071 = 7.1 VVE= VB+ VEB= 7.1 + 0.7 = 7.8 VFor the second circuit we can see that it is in cutoff mode. No current is flowing through thetransistor and thus IB= IC= IE= 0 and VB= VE= VEE= 15 V. VC= 0 V.For the third circuit we have VB= 0 V and VE= −0.7 V, and thusIE=VE− VEERE=−0.7 + 151= 14.3 mAit looks like the circuit is in saturation mode because of the very large ratio of RCand RE.In that case VC= VE+ VCEsat= −0.7 + 0.2 = −0.5 V, and thenIC=VCC− VCRC=15 + 0.5100= 0.16 mAThe large difference between ICand IEconfirms saturation
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