Introduction to Computer Engineering CS ECE 252 Fall 2007 Prof Mark D Hill Computer Sciences Department University of Wisconsin Madison Chapter 8 9 1 I O and Traps Copyright The McGraw Hill Companies Inc Permission required for reproduction or display I O Connecting to Outside World So far we ve learned how to compute with values in registers load data from memory to registers store data from registers to memory But where does data in memory come from And how does data get out of the system so that humans can use it 8 3 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display I O Connecting to the Outside World Types of I O devices characterized by behavior input output storage input keyboard motion detector network interface output monitor printer network interface storage disk CD ROM data rate how fast can data be transferred keyboard 100 bytes sec disk 30 MB s network 1 Mb s 1 Gb s 8 4 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display I O Controller Control Status Registers CPU tells device what to do write to control register CPU checks whether task is done read status register Data Registers CPU transfers data to from device Control Status CPU Output Data Graphics Controller Electronics display Device electronics performs actual operation pixels to screen bits to from disk characters from keyboard 8 5 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Programming Interface How are device registers identified Memory mapped vs special instructions How is timing of transfer managed Asynchronous vs synchronous Who controls transfer CPU polling vs device interrupts 8 6 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Memory Mapped vs I O Instructions Instructions designate opcode s for I O register and operation encoded in instruction Memory mapped assign a memory address to each device register use data movement instructions LD ST for control and data transfer 8 7 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Transfer Timing I O events generally happen much slower than CPU cycles Synchronous data supplied at a fixed predictable rate CPU reads writes every X cycles Asynchronous data rate less predictable CPU must synchronize with device so that it doesn t miss data or write too quickly 8 8 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Transfer Control Who determines when the next data transfer occurs Polling CPU keeps checking status register until new data arrives OR device ready for next data Are we there yet Are we there yet Are we there yet Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device Wake me when we get there 8 9 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LC 3 Memory mapped I O Table A 3 Location I O Register Function xFE00 Keyboard Status Reg KBSR Bit 15 is one when keyboard has received a new character xFE02 Keyboard Data Reg KBDR Bits 7 0 contain the last character typed on keyboard xFE04 Display Status Register DSR Bit 15 is one when device ready to display another char on screen xFE06 Display Data Register DDR Character written to bits 7 0 will be displayed on screen Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed in Chapter 10 8 10 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Input from Keyboard When a character is typed its ASCII code is placed in bits 7 0 of KBDR bits 15 8 are always zero the ready bit KBSR 15 is set to one keyboard is disabled any typed characters will be ignored 15 8 7 keyboard data 0 KBDR 1514 ready bit 0 KBSR When KBDR is read KBSR 15 is set to zero keyboard is enabled 8 11 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Basic Input Routine POLL NO Polling new char YES read character LDI R0 KBSRPtr BRzp POLL LDI R0 KBDRPtr KBSRPtr FILL xFE00 KBDRPtr FILL xFE02 8 12 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Simple Implementation Memory Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR KBDR 8 13 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Output to Monitor When Monitor is ready to display another character the ready bit DSR 15 is set to one 15 8 7 output data 0 DDR 1514 ready bit 0 DSR When data is written to Display Data Register DSR 15 is set to zero character in DDR 7 0 is displayed any other character data written to DDR is ignored while DSR 15 is zero 8 14 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Basic Output Routine POLL NO Polling screen ready YES write character LDI R1 DSRPtr BRzp POLL STI R0 DDRPtr DSRPtr FILL xFE04 DDRPtr FILL xFE06 8 15 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Simple Implementation Memory Mapped Output Sets LD DDR or selects DSR as input 8 16 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Keyboard Echo Routine Usually input character is also printed to screen User gets feedback on character typed and knows its ok to type the next character POLL1 POLL2 LDI BRzp LDI LDI BRzp STI R0 KBSRPtr POLL1 R0 KBDRPtr R1 DSRPtr POLL2 R0 DDRPtr NO YES read character KBSRPtr KBDRPtr DSRPtr DDRPtr FILL FILL FILL FILL xFE00 xFE02 xFE04 xFE06 new char NO screen ready YES write character 8 17 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Interrupt Driven I O External device can 1 Force currently executing program to stop 2 Have the processor satisfy the device s needs and 3 Resume the stopped program as if nothing happened Why Polling consumes a lot of cycles especially for rare events these cycles can be used for more computation Example Process previous input while collecting current input See Example 8 1 in text 8 18 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Interrupt Driven I O To implement an interrupt mechanism we need A way for the I O device to signal the CPU that an interesting event has occurred A way for the CPU to test whether the