Introduction to Computer EngineeringChapter 5 The LC-3Instruction Set ArchitectureLC-3 Overview: Memory and RegistersLC-3 Overview: Instruction SetOperate InstructionsNOT (Register)ADD/AND (Register)ADD/AND (Immediate)Using Operate InstructionsData Movement InstructionsPC-Relative Addressing ModeLD (PC-Relative)ST (PC-Relative)Indirect Addressing ModeLDI (Indirect)STI (Indirect)Base + Offset Addressing ModeLDR (Base+Offset)STR (Base+Offset)Load Effective AddressLEA (Immediate)ExampleControl InstructionsCondition CodesBranch InstructionBR (PC-Relative)Using Branch InstructionsSample ProgramJMP (Register)TRAPAnother ExampleFlow ChartProgram (1 of 2)Program (2 of 2)LC-3 Data Path RevisitedData Path ComponentsSlide 38Slide 39Slide 40Introduction to Computer EngineeringCS/ECE 252, Fall 2009Prof. Mark D. HillComputer Sciences DepartmentUniversity of Wisconsin – MadisonChapter 5The LC-3Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-3Instruction Set ArchitectureISA = All of the programmer-visible componentsand operations of the computer•memory organizationaddress space -- how may locations can be addressed?addressibility -- how many bits per location?•register sethow many? what size? how are they used?•instruction setopcodesdata typesaddressing modesISA provides all information needed for someone that wants towrite a program in machine language (or translate from a high-level language to machine language).Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-4LC-3 Overview: Memory and RegistersMemory•address space: 216 locations (16-bit addresses)•addressability: 16 bitsRegisters•temporary storage, accessed in a single machine cycleaccessing memory generally takes longer than a single cycle•eight general-purpose registers: R0 - R7each 16 bits widehow many bits to uniquely identify a register?•other registersnot directly addressable, but used by (and affected by) instructionsPC (program counter), condition codesCopyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-5LC-3 Overview: Instruction SetOpcodes•15 opcodes•Operate instructions: ADD, AND, NOT•Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI•Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP•some opcodes set/clear condition codes, based on result:N = negative, Z = zero, P = positive (> 0)Data Types•16-bit 2’s complement integerAddressing Modes•How is the location of an operand specified?•non-memory addresses: immediate, register•memory addresses: PC-relative, indirect, base+offsetCopyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-6Operate InstructionsOnly three operations: ADD, AND, NOTSource and destination operands are registers•These instructions do not reference memory.•ADD and AND can use “immediate” mode,where one operand is hard-wired into the instruction.Will show dataflow diagram with each instruction.•illustrates when and where data moves to accomplish the desired operationCopyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-7NOT (Register)Note: Src and Dstcould be the same register.Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-8ADD/AND (Register)this zero means “register mode”Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-9ADD/AND (Immediate)Note: Immediate field issign-extended.this one means “immediate mode”Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-10Using Operate InstructionsWith only ADD, AND, NOT…•How do we subtract?•How do we OR?•How do we copy from one register to another?•How do we initialize a register to zero?Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-11Data Movement InstructionsLoad -- read data from memory to register•LD: PC-relative mode•LDR: base+offset mode•LDI: indirect modeStore -- write data from register to memory•ST: PC-relative mode•STR: base+offset mode•STI: indirect modeLoad effective address -- compute address, save in register•LEA: immediate mode•does not access memoryCopyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-12PC-Relative Addressing ModeWant to specify address directly in the instruction•But an address is 16 bits, and so is an instruction!•After subtracting 4 bits for opcodeand 3 bits for register, we have 9 bits available for address.Solution:•Use the 9 bits as a signed offset from the current PC.9 bits:Can form any address X, such that: Remember that PC is incremented as part of the FETCH phase;This is done before the EVALUATE ADDRESS stage.255offset256 255PCX256PC Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-13LD (PC-Relative)Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-14ST (PC-Relative)Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-15Indirect Addressing ModeWith PC-relative mode, can only address data within 256 words of the instruction.•What about the rest of memory? Solution #1: •Read address from memory location,then load/store to that address.First address is generated from PC and IR(just like PC-relative addressing), thencontent of that address is used as target for load/store.Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-16LDI (Indirect)Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-17STI (Indirect)Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-18Base + Offset Addressing ModeWith PC-relative mode, can only address data within 256 words of the instruction.•What about the rest of memory?Solution #2:•Use a register to generate a full 16-bit address.4 bits for opcode, 3 for src/dest register,3 bits for base register -- remaining 6 bits are usedas a signed offset.•Offset is sign-extended before adding to base register.Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.5-19LDR (Base+Offset)Copyright © The