PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Future1Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Three Dimensional Integrated Circuits C.S. Tan, A. Fan, K.N. Chen, S. Das, N. Checka and R. ReifMicrosystems Technology LaboratoriesM.I.T.2Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 20033-D Integrated Circuits (3-D IC)A vertical stack of multiple device and interconnect layers connected together by interlayer vertical vias.Device/Interconnect LayerInterlayer Vertical Via3Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 20033-D IC with Cu-Cu Wafer Bonding(R. Reif, MIT)Interlayer Vertical ViaCu-Cu BondingM3M2M1M3M2M1M4DL2DL1DL – Device LayerM – Metal Interconnect Layer4Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003How Does 3-D Integration Help?•Greater number of nearest neighbors for a given transistor•Every transistor, gate, and module has increased wiring bandwidth•Interconnect distribution becomes shifted–Fewer global wires, more local wires•Energy consumption and cycle time reduced•More effective use of Si areaWire-lengthNumber of Interconnects(Log-Log Plot)2-D IC3-D IC5Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Digital Block Partitioning2DLogicMemorydwL3DLogicMemory<d<w<<L–Exploit locality to reduce interconnect lengths–Reduce chip area for interconnect-dominated applications–Increase density for device-dominated applications6Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Mixed-Signal PartitioningDigital Analog2D3DDigitalAnalog–Mixed-technology/mixed-signal based applications–Better signal isolation between analog and digital components7Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Monolithic integration of different diesBoarduPMemoryDSP RF3D2DMicroprocessorMemoryDSPRFBoard-Smaller form factor-Reduced power dissipation and/or energy consumption8Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 20033-D Approaches • Parallel fabrication, layer transfer by bonding - Dielectric : polymer, SiO2 - Metallic : Cu-Cu • Continuous layer growth/fabrication9Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Cu-Cu Wafer Bonding(R. Reif, MIT)Interlayer Vertical ViaCu-Cu BondingM3M2M1M3M2M1M4DL2DL1DL – Device LayerM – Metal Interconnect Layer10Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Crystallization of -SiBulk Sin+/p+n+/p+n+/p+GateGateT1T2M1M2M3M4n+/p+n+/p+Gaten+/p+M’1M’2VILICViaMemory orAnalogRecrystallized SiLogicRepeaters or optical I/O devices(K.Saraswat, Stanford)11Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 20033-D Research @ MIT• Process Technology Development• CAD Tool Development• Applications: 3-D Circuit/System- Partitioning Digital Circuits- Partitioning Mixed-Signal Circuits- Monolithically integrating several dies12Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Process Technology Development13Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003BOXM1 (Al)M1 (Al)LOCOS/STILOCOS/STICu ViaCu PadParallel FEOL Processes on 2 Device WafersDevice/Interconnect Layer 2 (SOI)Device/Interconnect Layer 1 (Bulk Si)14Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003•Handle wafer provides mechanical support and ease of wafer handling• Strong enough to withstand subsequent process• Ease of releaseSOI Wafer is attached to a handle waferSOI Wafer Thinning•SOI wafer etch back• A combination of mechanical grinding, plasma dry etch and chemical wet etch• Advantage of SOI – Etch stop on BOXCu Via and Pad formation•Via etch, passivation, barrier layer and fill• Cu Pad for bondingPrecision alignment and bonding15Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003• Optical alignment • Back-to-face bonding • Cu to Cu Bonding• Via pad is for electrical connection• Dummy pad is to increase bonding strengthPrecision alignment and bondingHandle Wafer Release• Fast process is required to minimize damage to the stack16Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Cu Contact BondingCu Contact Bonding 10 µm contact10 µm contact10 um contactSEM imageSEM imageTEM imageTEM imageSEM imageSEM imageSEM imageSEM image(K.N.Chen)17Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003CAD Tool Development18Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003FFT – Energy Consumption•27% - 40% reduction in switching energy•Can obtain almost all the energy savings while maintaining cycle time19Avogadro-Scale Engineering: Form and FunctionMIT, November 18, 19 2003Future•Introduce nanotubes/nanowires–Develop active/passive interconnects (wires that process and/or transmit information)–Develop insulators with high thermal conductivities (thermal profiles)–Develop nano-inductors (RF
View Full Document
Unlocking...