Three Dimensional Integrated Circuits C S Tan A Fan K N Chen S Das N Checka and R Reif Microsystems Technology Laboratories M I T Avogadro Scale Engineering Form and Function MIT November 18 19 2003 1 3 D Integrated Circuits 3 D IC A vertical stack of multiple device and interconnect layers connected together by interlayer vertical vias Interlayer Vertical Via Device Interconnect Layer Avogadro Scale Engineering Form and Function MIT November 18 19 2003 2 3 D IC with Cu Cu Wafer Bonding M3 M2 M1 Interlayer Vertical Via DL2 M4 Cu Cu Bonding M3 M2 M1 DL1 DL Device Layer M Metal Interconnect Layer Avogadro Scale Engineering Form and Function MIT November 18 19 2003 R Reif MIT 3 How Does 3 D Integration Help Avogadro Scale Engineering Form and Function MIT November 18 19 2003 Log Log Plot Number of Interconnects Greater number of nearest neighbors for a given transistor Every transistor gate and module has increased wiring bandwidth Interconnect distribution becomes shifted Fewer global wires more local wires Energy consumption and cycle time reduced More effective use of Si area 2 D IC 3 D IC Wire length 4 Digital Block Partitioning Logic Memory L L Memory Logic w d 2D w d 3D Exploit locality to reduce interconnect lengths Reduce chip area for interconnect dominated applications Increase density for device dominated applications Avogadro Scale Engineering Form and Function MIT November 18 19 2003 5 Mixed Signal Partitioning Analog Digital Analog Digital 2D 3D Mixed technology mixed signal based applications Better signal isolation between analog and digital components Avogadro Scale Engineering Form and Function MIT November 18 19 2003 6 Monolithic integration of different dies Microprocessor Memory RF DSP Memory DSP uP RF Board Board 2D 3D Smaller form factor Reduced power dissipation and or energy consumption Avogadro Scale Engineering Form and Function MIT November 18 19 2003 7 3 D Approaches Parallel fabrication layer transfer by bonding Dielectric polymer SiO2 Metallic Cu Cu Continuous layer growth fabrication Avogadro Scale Engineering Form and Function MIT November 18 19 2003 8 Cu Cu Wafer Bonding M3 M2 M1 Interlayer Vertical Via DL2 M4 Cu Cu Bonding M3 M2 M1 DL1 DL Device Layer M Metal Interconnect Layer Avogadro Scale Engineering Form and Function MIT November 18 19 2003 R Reif MIT 9 Crystallization of Si Repeaters or optical I O devices Gate n p n p VILIC M4 M3 M2 M1 Gate Recrystallized Si n p n p T2 Memory or Analog M 2 M 1 Gate Via n p n p Bulk Si Avogadro Scale Engineering Form and Function MIT November 18 19 2003 T1 Logic K Saraswat Stanford 10 3 D Research MIT Process Technology Development CAD Tool Development Applications 3 D Circuit System Partitioning Digital Circuits Partitioning Mixed Signal Circuits Monolithically integrating several dies Avogadro Scale Engineering Form and Function MIT November 18 19 2003 11 Process Technology Development Avogadro Scale Engineering Form and Function MIT November 18 19 2003 12 Parallel FEOL Processes on 2 Device Wafers M1 Al LOCOS STI Device Interconnect Layer 2 SOI BOX Cu Pad Cu Via M1 Al LOCOS STI Avogadro Scale Engineering Form and Function MIT November 18 19 2003 Device Interconnect Layer 1 Bulk Si 13 Cu Via andalignment Pad formation Precision and SOI Wafer Thinning SOI Wafer is attached bonding etch to Via a handle wafer SOI waferpassivation etch back barrier layer and fill Handle A combination wafer provides of mechanical mechanical Cu Pad support for grinding bonding and ease of wafer handling plasma dry etch and chemical Strong enough withstand wettoetch subsequent process Advantage of SOI Etch stop on BOX Ease of release Avogadro Scale Engineering Form and Function MIT November 18 19 2003 14 Precision alignment and Handle Wafer Release bonding Fast process is required to minimize damage to the Optical alignment stack Back to face bonding Cu to Cu Bonding Via pad is for electrical connection Dummy pad is to increase bonding strength Avogadro Scale Engineering Form and Function MIT November 18 19 2003 15 Cu Contact Bonding SEM SEMimage image SEM SEMimage image 10 um contact SEM SEMimage image 10 10 m m contact contact TEM TEMimage image K N Chen Avogadro Scale Engineering Form and Function MIT November 18 19 2003 16 CAD Tool Development Avogadro Scale Engineering Form and Function MIT November 18 19 2003 17 FFT Energy Consumption 27 40 reduction in switching energy Can obtain almost all the energy savings while maintaining cycle time Avogadro Scale Engineering Form and Function MIT November 18 19 2003 18 Future Introduce nanotubes nanowires Develop active passive interconnects wires that process and or transmit information Develop insulators with high thermal conductivities thermal profiles Develop nano inductors RF applications Avogadro Scale Engineering Form and Function MIT November 18 19 2003 19
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