Implementation of Large Memory Chips Consider a 4M x 4 bit chip which has a 22 bit addresses since 4M 222 Logically Externally we view a 4M x 4 bit memory as pictured below with each memory word made up of four bits b3 b2 b1 b0 Decimal Address 0 1 2 3 b3 b2 b1 b0 22 2 1 When we want to read a word we supply a 22 bit address and receive the corresponding 4 bit word The register file implementation see handout does not scale well for large memories for several reasons the number of gates in the address decoder and MUXs grows exponentially with the number of bits in the address lots of wires into out of the memory chip for address data and control These problems are solved by using square array of bits and decoding the address in two parts row then column number eliminate MUX s by using tri state buffers single port RAM memory data wires shared for reading and writing Square Memory 1 b2 b1 b0 Row 0 Row 0 b3 Row 0 Decimal Address 0 1 2 3 Row 0 To help us see how the 4M x 4 bit memory gets mapped to the 2048 x 2048 x 4 memory array on the next page consider splitting memory into 2048 word blocks as shown below Row 2047 Row 2047 Row 2047 Row 2047 22 11111111111 00000000000 00000000001 00000000010 00000000011 00000000001 00000000010 00000000010 00000000010 00000000010 11111111111 00000000000 00000000001 00000000010 00000000011 00000000010 00000000011 11111111111 00000000000 Row 2 Row 2 Row 2 Row 2 4095 4096 4097 4098 4099 2 1 00000000000 00000000001 00000000001 00000000001 00000000001 Row 1 Row 1 Row 1 Row 1 2047 2048 2049 Binary Address Location in Row Row 00000000000 00000000000 00000000000 00000000001 00000000000 00000000010 00000000000 00000000011 11111111111 11111111111 11111111111 11111111111 00000000000 00000000001 00000000010 00000000011 11111111111 11111111111 Square Memory 2 Each bit of a word is split into a separate 2048 x 2048 square memory array Each of these square memory arrays is 2048 x 2048 211 x 211 222 4M bits The 22 bit address of the 4M memory is split into two 11 bit parts The upper 11 bits is first used to activate the correct row within the square memory arrays Of the 2048 bit row that is read from each memory array we are interested in only one bit The lower 11 bits of the address specifies the location of the desired bit within the 2048 bit row Bit b 0 Row 0 Row 1 2048 x 2048 2048 x 2048 Row 2047 Row 2047 0 1 11 to 2048 Decoder Bit b 1 Row 0 Row 1 0 1 2047 Bit b 2 11 to 2048 Decoder Bit b 3 2047 Sense Amplifier and I O Gate 11 Data Data Input Output Buffer Buffer Amp I O Gate Amp I O Gate DIB DOB DIB DOB Sense Amplifier and I O Gate Data Data Input Output Buffer Buffer 11 D3 22 bit Address 11 bit Row 11 bit Column D2 D1 D0 Note This is a tri state three state buffer It acts as a switch When the Control is a In 1 the In signal is passed to the the Out wire When the Control Control is a 0 the In is disconnected from the Out wire Out Square Memory 3 Implementing Large Memory with Smaller Chips Consider for example implementing 4M x 32 bits memory with 256KB x 1 bit chips The 256KB x 1 chips are implemented as square arrays of 512 x 512 We will use an two dimensional array of the 256KB x 1 chips to implement the larger memory The number of chips per row would be 32 bits 1 bit 32 chips The number of chips per column would be 4M 256K 222 218 24 16 chips per column The 22 bit address of the 4M x 32 bit memory would be split up as follows 22 bit Address 4 bits 18 bits chip row column row within chip within chip 9 bits 9 bits time multiplexed 9 4 0 4 to 16 1 Decoder 15 32 chips in a row 512 x 512 chip Out CS 512 x 512 chip 512 x 512 chip Out CS 512 x 512 chip Row 0 of Chips CS Row 1 of Chips CS 512 x 512 chip CS 512 x 512 chip CS 512 x 512 chip Out CS CS means Chip Select Row 15 of Chips 512 x 512 chip CS b 31 b 30 512 x 512 chip CS b0 Square Memory 4