Name Homework 2 Computer Organization Due Febuary 11 2011 F 1 Recall that the sum of products SOP Boolean formula for the carry out ci 1 of a 1 bit adder was ci 1 xi yi xi ci yi ci a Complete the following table showing the gate delays for different types of adders assuming a 9 input limit into any gate Type of product terms Most of inputs in any of in SOP expression of the product terms Adder to be OR ed 1 bit 3 2 2 bit 7 3 3 bit 15 4 4 bit 31 5 5 bit 63 6 6 bit 127 7 7 bit 255 8 8 bit 511 9 9 bit 1 023 10 gate delays due gate delays to product AND due to sum OR terms 1 b Consider the SOP Boolean formula for the carry out ci 9 of a 9 bit adder x i 8 y i 8 x i 7 y i 7 x i 3 y i 3 x i 2 y i 2 Gate Delay per Adder 1 x i 1 y i 1 2 xi yi c i 9 ci Give an example of each of the following i a product term with only two terms ii a product term with 10 terms HW 3 Page 1 Name 2 Complete the below diagram of a 4 bit register so that it is able to perform the following operations parallel read output of all bits just look at the Q values Control the MUXs using the following codes 002 parallel write input of all bits 012 circular shift left one bit position value shifted out of most significant bit is shifted into the least significant bit 102 arithmetic shift right sign extend the most significant bit 112 logical shift right one bit position value shifted out of least significant bit is lost and a 0 is shifted into the most significant bit Note For each D flip flop the output of a MUX is used as the D input Data to Write in Parallel Control 2 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX D D D D Q Q Q Q Load Data to Read in Parallel HW 3 Page 2
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