Supplement for Assignment 5 section 3 6 of the textbook The most basic 1 bit memory is the SR latch with consists of two cross coupled NOR gates R Q S Recall the NOR gate truth table Q A 0 0 1 1 B 0 1 0 1 A B 1 0 0 0 The S stands for Set to remember 1 and the R for Reset to remember 0 For example if the input values of R 0 and S 1 are held constant then the bottom NOR gate will start outputting 0 This 0 is fed as an input to the upper NOR with the R 0 so both of the upper NOR gate s inputs are 0 Thus the upper NOR gate will start outputting a 1 which is fed back to the bottom NOR as an input Now the bottom NOR has an input of two 1 s but it continues to output a 0 because that s what NORs do see truth table If the S input s value is now changed back to 0 both R 0 and S 0 then bottom NOR will continue to output 0 i e Q 0 since the top NOR is still outputting a 1 The top NOR has two 0 inputs so it continues to output 1 i e Q 1 This is a stable state where the SR latch is remembering a 1 A timing diagram for the above scenario would look like time R S one gate delay Q Q one gate delay 1 Initial state of R 0 and S 1 2 After a gate delay the bottom NOR outputs a 0 which is fed to the upper NOR the upper NOR has two 0s for inputs 3 After a gate delay the top NOR outputs a 1 which is fed to the bottom NOR the bottom NOR has two 1s for inputs 4 When S returns to 0 no change in outputs The SR latch is actual symmetric from top to bottom so a similar argument can be made for the inputs of R 1 and S 0 causing a stable state of it remembering a 0 The main problem with the SR latch is that its output changes are determined by some number of gate delays after its inputs are changed This makes it difficult for a collection of one bit memories to work in a lock step fashion to hold a multiple bit value It also has the problem that inputs of R 1 and S 1 lead to an undefined state Memory Supplement Page 1 Supplement for Assignment 5 section 3 6 of the textbook We can solve these problems in a series of steps First we ll add a Clock input to prevent the memory from changing states if the Clock 0 This leads us to a clocked SR latch R R Q Clock S Q S Original SR latch When the Clock 0 both AND gates will output 0s This guarantees that the original SR latch has inputs of R 0 and S 0 so it cannot change its memory state When the Clock 1 the AND gates allow the R and S inputs to be passed through without change This does not exactly solve either of the previously mentioned problems but we can at least prevent the clocked SR latch from changing by having the Clock 0 To solve the problem of inputs of R 1 and S 1 leading to an undefined state We ll consider a slightly different clocked latch called a clocked D latch The clocked D latch remembers the value on the D input when the Clock 1 If the Clock 0 then the D input is ignored and the one bit memory is not changed The clocked D latch circuit is very similar to the clocked SR latch D R Q Clock S Q Original SR latch To fix the problem of the one bit memory having its output changing being determined by some number of gate delays after its inputs are changed We can use two clocked D latches to build a Master Slave D flip flop which changes state only on the falling edge of the clock pulse The below timing diagram shows how the internal clocked D latches change within the master slave flip flop to achieve this When the Clock 1 the master D latch can change to D s value but the slave D latch cannot change since it receives the negated Clock signal of 0 When the Clock 0 the master D latch cannot change but the slave D latch can change to remember the value being remembered in the master D latch Qm Memory Supplement Page 2 Supplement for Assignment 5 section 3 6 of the textbook D Clock D Q Clk Q Qm D Q Clk Q Qs Q Q time Clock D Qm Q Qs The value of Q only changes on the falling edge of the Clock This master slave D flip flop allows for a collection of one bit memories to work in a lock step fashion to hold a multiple bit value The value currently contained in a D flip flop can to read from the slave s Q in the same clock pulse as a new value is written to it into the master s D input The following block diagram shows how four D flip flops can be used to load and read 4 bit value in parallel The triangle input of each flip flop connected to the Load wire is the Clock input in the above diagram This triangle input indicates that a flip flop is being used instead of a latch Data to Write in Parallel Load D D D D Q Q Q Q Data to Read in Parallel Memory Supplement Page 3 Supplement for Assignment 5 section 3 6 of the textbook Another more complex example would be a shift register that allows the value stored in the register to also be shifted by one bit position several ways The below diagram is a 4 bit shift register that is able to perform the following operations parallel read output of all bits just look at the Q values Control of 002 parallel write input of all bits Control of 012 logical shift left one bit position value shifted out of most significant bit is lost and a 0 is shifted into the least significant bit Control of 102 circular shift right one bit position value shifted out of least significant bit is shifted into the most significant bit Control of 112 arithmetic shift right sign extend the most significant bit For each D flip flop the output of a MUX is used as the D input The Control wires control the MUXs to vary the value routed to the D inputs Data to Write in Parallel 0 Control 2 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX D D D D Q Q Q Q Load Data to Read in Parallel Register File Computers typically have a collection of registers called a …