Homework 5 Computer Organization Due Friday 10 5 1 Complete the below diagram of a 4 bit register so that it is able to perform the following operations parallel read output of all bits just look at the Q values parallel write input of all bits logical shift left one bit position value shifted out of most significant bit is lost and a 0 is shifted into the least significant bit circular shift right one bit position value shifted out of least significant bit is shifted into the most significant bit arithmetic shift right sign extend the most significant bit Note For each D flip flop the output of a MUX is used as the D input Data to Write in Parallel Control 2 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX 0 1 2 3 MUX D D D D Q Q Q Q Load Data to Read in Parallel 2 Using the discussion in the book and the register file handout draw a complete not just a one bit slice register file that has 4 registers 3 bits per register one write port two read ports You can draw block diagrams for flip flops decoders and MUXs without showing their gate implementations but you should show all the flip flops decoders MUXs and connecting wires 3 How well does this register file design scale Suppose that we are implementing a 16 M x 8 16M registers each with 8 bits register file with one write port and one read port a How many and what type of decoder s would be needed b How many total gates assume 9 input limit on AND OR gates would be needed to implement this these decoder s c How many and what type of MUX s would be needed d How many total gates assume 9 input limit on AND OR gates would be needed to implement this these MUX s e Assuming D flip flops to store each bit 5 gates flip flop What of the total gates is used to implement the D flip flops 4 Redo the previous question using the 16 M x 8 square memory implementation similar to the Implementation of Large Memory Chips class handout
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