AspenAspen: ObjectivesBasic LayoutCore LayoutNode LayoutCore ImplementationNode ImplementationNode ExampleMC68HC908GZ16 Specification SheetSoftware processesMemory MapProblems EncounterCost SheetScheduleDivision of LaborQuestionsAspenGarrett EarnshawJoe ChmuraMieszko KrugerYoni MekuriaAspen: ObjectivesTo dynamically control a network of peripheral devices, a network that controls as well as senses with the use of a CAN bus.GarrettBasic LayoutGarrettCore LayoutGarrettNode LayoutGarrettCore Implementation Parts and Logic diagramJoeMC68HC908GZ16MC33388MM74C9224x4 KeypadOptrex LCDNode Implementation Parts and Logic diagramJoeMC68HC908GZ16MC33388Node ExampleJoeMC68HC908GZ16Specification SheetHigh-performance M68HC08 architecture optimized High-performance M68HC08 architecture optimized for C-compilers for C-compilers 8-MHz internal bus frequency 8-MHz internal bus frequency 16k Flash16k Flash1k RAM1k RAM408 bytes of ROM408 bytes of ROMMSCAN08 (Motorola scalable controller area MSCAN08 (Motorola scalable controller area network, implementing 2.0b protocol)network, implementing 2.0b protocol)MieszkoSoftware processes Core Operational Core Operational DiagramDiagramNode Operational Node Operational DiagramDiagramMieszkoMemory Map Address Description $0000-$003F I/O Registers 64 bytes $0040-$0440 RAM 1024 bytes $0440-$04FF Unimplemented 192 bytes $0500-$057F MSCAN08 Control and Message Buffer 128 bytes $0580-$1BFF Unimplemented 5760 bytes $1C00-$1D95 Flash Programming Routines ROM 406 bytes $1D96-$BFFF Unimplemented 41,578 bytes $C000-$FDFF Flash Memory 15,872 bytes $FE00 Break Status Register (BRS) 1 byte $FE01 SIM Reset Status Register (SRSR) $FE02 Break Auxiliary Register (BRKAR) $FE03 Break Flag Control Register (BFCAR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 Flash Control Register (FLCR) $FE09 Break Address Register High (BRKH) $FE0A Break Address Register Low (BRKL) $FE0B Break Status and Control Register (BRKSCR) $FE0C LVI Status Register (LVISR) $FE0D-$FE0F Unimplemented 3 bytes $FE10-$FE1F Unimplemented 16 bytes Reserved for Compatibility with Monitor Code for A-Family Part $FE20-$FF7D Monitor Rom 350 bytes $FF7E Flash Block Protect Register (FLBPR) $FF7F-$FFD3 Unimplemented 85 bytes $FFD4-$FFFF Flash Vectors 44 bytes MieszkoProblems EncounterColdfire development board = overkill. Redesign our core board.Licensing issues with CodeWarrior.MieszkoCost SheetItem Quantity Price (per unit) Total per Item(s)Standard AT power supply 1 $26.87 $26.87RS232 Cable Male-Female 1 $13.49 $13.49Quad Flat Pack Adapter 48QFS30-D6-SMT-S2 $24.00 $48.00MC68HC908GZ16 48 lead QFP MCU6 Donated DonatedMC33388 CAN Physical Layer Interface Chip6 Donated DonatedMONO8 Connectors2 Donated DonatedSimulator or emulator softwareDonated Donated16 Key Keypad1 $20.82 $20.828 MHz Crystals6 $0.94 $5.64Miscelaneous Partsas needed $50.00 $50.00Total Cost$164.82Estimated Core Cost $50.19Estimated Node Cost $5-$15YoniScheduleYoniDivision of LaborGarrettGarrettCore design and buildCore design and buildSoftwareSoftwareDocumentationDocumentationJoeJoePowerPowerLeaf design and buildLeaf design and buildYoniYoniPowerPowerLeaf implementationLeaf implementationCabling Cabling MieszkoMieszkoSoftwareSoftwareCommunication Communication with leaveswith
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