Kabuki 2800AgendaOVERVIEW Design goalProject overview Target consumerProject overview Current statusProject overview Kabuki 2800 baseline requirementsProject overview Kabuki 2800 secondary requirementsBlock DiagramIMPLEMENTATIONEffects (on DSK)I/O CardSlide 12Slide 13Performance ModuleDSP Co-processor TMS3206713B-200Touch Screen Motion Computing M1300Development StructureDan’s TasksJustin’s TasksTim’s TasksYazan Task’sSchedulePhasesPerformance Board Phase 1Performance Board Phase 2I/O Board Phase 3Slide 27Slide 28Performance Board Phase 3DSP Coprocessor Phase 1DSP Coprocessor Phase 2DSP Coprocessor Phase 3Effect Algorithms Phase 1Effect Algorithms Phase 2Effect Algorithms Phase 3RISKS AND CONTINGENCY PLANUSB FIFO InterfaceRS-232 InterfaceDSP co-processorTouch-screen InterfaceKabuki 2800“a real-time digital audio effects system for performance”team “Big Country” presentsECEN4610 Preliminary Design Review14 September 2006Agenda1. Project overview2. Architecture3. Implementation4. Risk management5. Division of labor6. ScheduleOVERVIEWDesign goalCustomizeable and extensible real-time digital audio effects system for live performanceProject overviewTarget consumerLive performance!Electronic composersElectronic musiciansMic’ed acoustic musiciansProject overviewCurrent statusKabuki 1200Summer ‘06Some effectsSlider inputNo custom effectsSlow displayProject overviewKabuki 2800 baseline requirementsComputer control+display interfaceSupport for saved presetsCustom effectsTime-domain base effectsPortableProject overviewKabuki 2800 secondary requirementsInterchangeable human input boardFFT coprocessor for performanceFrequency-domain effectsBlock Diagram Kabuki 2800Summer ProgressIMPLEMENTATIONHow is it all going to work?1. Effects2. I/O Card3. Touchscreen4. Performance Module5. DSP Co-ProcessingXX XXX XX X X S F HEffects (on DSK) Filter and Equalizer FIR IIR  Echo & ReverbBuffering FlangeFancy Buffering GranulationCrazy Buffering Pitch Time Shifting-FFT and/or wavelet transform Etc..I/O CardEMIFComputerInterruptsI/O CardFPGA Altera Cyclone I/II3-8ns propogationlow-costFIFO “MegaFunction”Clock Source: buffered clock from EMIFUSB:DLP Designs USB to parallel module(USB Control Cores for FPGAs)RS-232• MAX3232• 1Mbit/s• 2Tx & 2RxEMIF bus: (drive and voltage change)•MAX3000E• Converts voltage levels from 1.2 <-> 5.5 VoltsMostly PCB and some Wire-WrapI/O CardPerformance ModuleFPGA to handle communication and device polling.4-5 foot buttons• (Directly into logic device)1-2 Pedals• Pedals act as attenuators• Feed 5V signal• AD7861 (ADC with 11bit resolution)•Low speed• PLCC 44 packageClock Source: Crystal Oscillator (1MHz)DSP Co-processorTMS3206713B-200200pin HLQFP•Not BGA!!!Connection• through Host Peripheral Interface on DSK192K internal SRAM• Maybe enough!Clock Source:•same as DSK, 50MHz Crystal Oscillator.HPITouch ScreenMotion Computing M1300Slate style tablet: large screenLinuxPreset ProgrammingSlider DisplayDevelopment Structure Primary Secondary Kabuki 2800Dan’s TasksPrimary Software EffectsSoftware DevicesSoftware simulation Secondary  Layout design and fabrication.  Firmware Kabuki 2800Justin’s TasksPrimary  I/O Layout Design and Fabrication Firmware  USB design and ProtocolsSecondary Does No have any. Kabuki 2800Tim’s TasksPrimary Performance board firmware layout and design Kabuki 2800 Secondary USB Design and Protocols Device CasingYazan Task’sPrimary Device Casing and FabricationDSK and interface Card Kabuki 2800 Secondary Module hardware designModule Firmware designAudio effect algorithm simulationAudio effect algorithmFinal packaging and SoftwarePhase 1 – Milestone 1, Nov. 2Phase 2 – Milestone 2, Nov. 30Phase 3 – Expo, Dec. 14ScheduleSchedulePhasesPhasesPhase 1 – Development & PrototypingPhase 2 – IntegrationPhase 3 – Testing and ProductionFPGA configuredFPGA boots from EEPROMFLASH reads/writes properlyDSK I/O Firmware CompleteUSB testedRS-232 interface testedPerformance BoardPerformance BoardPhase 1FPGA configured and tested Performance BoardPerformance BoardPhase 2All interfaces fully functional (RS-232, USB)Flash storage able to load / store presetsI/O functions with DSK and DSP co-processorUSB firmware interfaces with FPGA and with host computerRS-232 interface fully functioningFirmware completed and under testingCommunication established with DSP coprocessor.I/O BoardI/O BoardPhase 3FPGA configured and testedFPGA boots from EEPROMA/D converter testedFirmware in testingPerformance BoardPerformance BoardPhase 1FPGA interfaces with I/O board Foot – pedals generate interruptsA/D converter samples fader pedalPerformance BoardPerformance BoardPhase 2FPGA interfaces with Interface Card All user inputs are fully functionalPerformance BoardPerformance BoardPhase 3Board Layout CompleteDSP Coprocessor DSP Coprocessor Phase 1Board fabricated, populated and ready for testingJTAG readyDSP Coprocessor DSP Coprocessor Phase 2DSP Processor is able to implement FFT and Wavelet TransformsDSP is able to communicate with I/O board and and co-process transformsDSP Coprocessor DSP Coprocessor Phase 3Effect Algorithms Effect Algorithms Phase 1Time Domain Effects SimulatedPhasingFiltersEtc.Most time domain effects simulatedSeveral more time domain effects implementedFFTs simulated in MatlabEffect Algorithms Effect Algorithms Phase 2Time Domain effects implementedFFT and Wavelet Domain effects simulated and implementedEffect Algorithms Effect Algorithms Phase 3RISKS AND RISKS AND CONTINGENCY PLANCONTINGENCY PLANSources of RiskUSB interfaceRS-232 interfaceDSP co-processorTouch-screen interfaceUSB FIFO InterfaceUSB FIFO InterfaceRISKS:Needs Windows DLLs to be recognizedMust interface with FPGATimingCONTINGENCY PLANUSE RS-232USE Preprogrammed Flash MemoryRS-232 InterfaceRS-232 InterfaceRISKSCommunication is not fast enoughTimingCONTINGENCY PLANMake the performance board stackable on top of the existing DSKDSP co-processorDSP