Loran-C ReceiverAgendaBudgetBlock DiagramOutline of ApproachAntenna/ReceiverSignal Processing Unit Part ListProcessor SchematicFPGA DesignFPGA SchematicFPGA – Chip SelectSoftware DesignSlide 13Slide 14Progress since PDRProject TimelineFuture DeadlinesMilestone 1Milestone 2Capstone ExpoExtra FeaturesDivision of LaborQuestions/CommentsLoran-C ReceiverLoran-C ReceiverTeam Deathstar:Team Deathstar: Christopher BirschbachChristopher BirschbachMatthew HaymanMatthew HaymanMatthew AndersonMatthew AndersonChristina CornerChristina CornerErin MowbrayErin MowbrayOctober 5, 2004ECEN 4610 Capstone ECEN 4610 Capstone CDRCDRAgendaAgendaBudgetBudgetSystem DiagramSystem DiagramSubsystem FunctionalitySubsystem Functionality–Hardware/SchematicsHardware/Schematics–Parts ListParts List–Software DesignSoftware DesignProgress since PDRProgress since PDRFuture Goals and Future Goals and DeadlinesDeadlines–Milestone 1Milestone 1–Milestone 2Milestone 2–ExpoExpoDivision of LaborDivision of LaborQuestions/CommentsQuestions/CommentsBudgetBudgetItemItemDescriptionDescriptionEstimated PriceEstimated PriceProcessorProcessor$100.00$100.00LCD DisplayLCD Display11$75.00$75.00Additional memoryAdditional memory11$50.00$50.00A to D converterA to D converter11$50.00$50.00Antenna AssemblyAntenna Assembly11$100.00$100.00Receiver EnclosureReceiver Enclosure11$100.00$100.00Printed Circuit BoardPrinted Circuit Board11$200.00$200.00FPGAFPGAXilinx FPGA Evaluation KitXilinx FPGA Evaluation Kit$250.00$250.00FiltersFilters 3 Butterworth (8th order)3 Butterworth (8th order)$75.00$75.00RS-232 InterfaceRS-232 Interface11$25.00$25.00Support ElectronicsSupport ElectronicsResistors, Caps, switches, sockets, cablesResistors, Caps, switches, sockets, cables$150.00$150.00Power SupplyPower Supply11$100.00$100.00Student Designed User ManualStudent Designed User ManualWeighted Paper, Binding, Printing CostsWeighted Paper, Binding, Printing Costs$150.00$150.00Final Project DisplayFinal Project DisplayPrinted Poster for Engineering ExpoPrinted Poster for Engineering Expo$100.00$100.00Loran C User HandbookLoran C User Handbook11$25.00$25.00Misc. Misc. (Ink Cartridges, Repair parts, reference (Ink Cartridges, Repair parts, reference manuals)manuals)$200.00$200.0011TOTAL:TOTAL:$1,750.00$1,750.00Block DiagramBlock DiagramOutline of ApproachOutline of ApproachThe system will consist of the following The system will consist of the following subsystems:subsystems:–Antenna ReceiverAntenna Receiver–Analog-to-digital converter Analog-to-digital converter –Motorola 68HC11 processorMotorola 68HC11 processor–MemoryMemory–FPGAFPGA–Serial Interface Serial Interface –PCPC–PowerPowerAntenna/ReceiverAntenna/ReceiverAM Antenna8th Order Butterworth Filter (MAX274B)(This portion of the project will continue when the filters from Maxim arrive.)Signal Processing Signal Processing Unit Unit Part ListPart ListParts List Part NumberMotorola Processor 68HC11Flash AT29C256Bi-directional drivers 74HC245Latch 74HC373Schmitt trigger inverter 74HC14Xilinix FPGA XCS10FPGA EPROM XC18V256RAM HM622563.3V regulator 78M335V regulator 7805A/D Converter AD7828RS-232 Adapter MAX233TTL AND gate 74LS088 MHz clock CO6050Processor SchematicProcessor SchematicFPGA DesignFPGA DesignChip selectChip selectState machineState machineCounterCounterFPGA SchematicFPGA SchematicFPGA – Chip SelectFPGA – Chip SelectSoftware DesignSoftware DesignFPGA:FPGA:–InputInputDigital Loran-C signalDigital Loran-C signal–OutputOutputCounter DataCounter DataProcessor:Processor:–InputInputCounter DataCounter Data–OutputOutputTime delaysTime delaysPC:PC:–InputInputTime delaysTime delays–OutputOutputLatitudinal and Longitudinal coordinatesLatitudinal and Longitudinal coordinatesSoftware DesignSoftware DesignInitial Test CodeInitial Test CodeSoftware DesignSoftware DesignProgress since PDRProgress since PDRSchematic DesignSchematic DesignInitial Wire wrapped Initial Wire wrapped board completedboard completedBasic Processor Basic Processor FunctionalityFunctionalityBasic FPGA Basic FPGA FunctionalityFunctionalityBasic RAM Basic RAM FunctionalityFunctionalityProject TimelineProject TimelineFuture DeadlinesFuture DeadlinesMilestone 1 – 10/26Milestone 1 – 10/26Milestone 2 – 11/16Milestone 2 – 11/16Open-Lab Expo – Open-Lab Expo – 12/912/9Milestone 1Milestone 1Date: October 26Date: October 26ththParts completed: Parts completed: –Completed Wiring on Vector Board Completed Wiring on Vector Board –Antenna/Filtering –Clean signalAntenna/Filtering –Clean signal–Sampling by A/D converter Sampling by A/D converter completedcompleted–Order first PCBOrder first PCBMilestone 2Milestone 2Date: November 16Date: November 16ththParts Completed:Parts Completed:–Functioning PCBFunctioning PCB–State machine on FPGA workingState machine on FPGA working–Communication between the Communication between the Processing Unit and Processing Unit and Antenna/Receiver.Antenna/Receiver.Capstone ExpoCapstone ExpoWorking Loran-C Working Loran-C ReceiverReceiver–Functionality between all Functionality between all 3 Subsystems: 3 Subsystems: Antenna/Receiver, Antenna/Receiver, Processing Unit, & PCProcessing Unit, & PC–Working Serial Working Serial InterfaceInterfaceExtra FeaturesExtra FeaturesThese will be added if time These will be added if time permits at the end of the permits at the end of the semester.semester.–Portable Power SupplyPortable Power Supply–LCD DisplayLCD DisplayDivision of LaborDivision of LaborMatt AMatt A–PowerPower–Memory interfaceMemory interface–Microprocessor ProgrammingMicroprocessor ProgrammingChris BChris B–PC programmingPC programming–Microprocessor programmingMicroprocessor programming–User’s ManualUser’s ManualChristy CChristy C–Antenna/FilteringAntenna/Filtering–Verilog DesignVerilog Design–User’s ManualUser’s ManualMatt HMatt H–Antenna/FilteringAntenna/Filtering–PCB PCB –Microprocessor ProgrammingMicroprocessor Programming–PC programmingPC programmingErin MErin M–Verilog DesignVerilog Design–User’s ManualUser’s Manual–PC interfacePC